AD7453BRT-R2 datasheet(15/21 Pages) AD

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AD7453

Rev. B | Page 14 of 20

Timing Example 1

Sixteen serial clock cycles are required to perform a conversion

and to access data from the AD7453. CS going low provides the

first leading zero to be read in by the microcontroller or DSP.

The remaining data is then clocked out on the subsequent

SCLK falling edges, beginning with the second leading zero.

Thus the first falling clock edge on the serial clock provides the

second leading zero. The final bit in the data transfer is valid on

the 16th falling edge, having been clocked out on the previous

(15th) falling edge. Once the conversion is complete and the data

has been accessed after the 16 clock cycles, it is important to

ensure that, before the next conversion is initiated, enough time

is left to meet the acquisition and quiet time specifications. See

Timing Example 1.

Having FSCLK = 10 MHz and a throughput rate of 555 kSPS gives

a cycle time of

1/Throughput = 1/555,000 = 1.8 µs

A cycle consists of

t2 + 12.5(1/FSCLK) + tACQ = 1.8 µs

Therefore if t2 = 10 ns,

10 ns + 12.5(1/10 MHz) + tACQ = 1.8 µs

tACQ = 540 ns

This 540 ns satisfies the requirement of 290 ns for tACQ. From

Figure 23, tACQ comprises

In applications with a slower SCLK, it may be possible to read in

data on each SCLK rising edge, i.e., the first rising edge of SCLK

after the CS falling edge would have the leading zero provided,

and the 15th SCLK edge would have DB0 provided.

2.5(1/FSCLK) + t8 + tQUIET

where t8 = 35 ns. This allows a value of 255 ns for tQUIET,

satisfying the minimum requirement of 60 ns.

tCONVERT

SCLK

12.5(1/FSCLK)

tACQUISITION

1/THROUGHPUT

tQUIET

10ns

Figure 23. Serial Interface Timing Example

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