FDMF6840C datasheet(16/19 Pages) ONSEMI

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PCB Layout Guidelines

Figure 31 and Figure 32 provide an example of a proper

layout for the FDMF6840C and critical components. All

of the high-current paths, such as V IN, VSWH, VOUT,

and GND copper, should be short and w ide for low

inductance and resistance. This aids in achieving a

more stable and evenly distributed current flow , along

w ith enhanced heat radiation and system performance.

Recommendations for PCB Designers

1. Input ceramic bypass capacitors must be placed

close to the V IN and PGND pins. This helps reduce

the high-current pow er loop inductance and the input

current ripple induced by the pow er MOSFET

sw itching operation.

2. The VSWH copper trace serves tw o purposes. In

addition to being the high-frequency current path

from the Dr MOS package to the output inductor, it

serves as a heat sink for the low -side MOSFET in

the Dr MOS package. The trace should be short and

w ide enough to present a low -impedance path for

the high-frequency, high-current flow betw een the

Dr MOS and inductor. The short and w ide trace

minimizes electrical losses as w ell as the Dr MOS

temperature rise. Note that the VSWH node is a high-

voltage and high-frequency sw itching node w ith high

noise potential. Care should be taken to minimize

coupling to adjacent traces. Since this copper trace

acts as a heat sink for the low er MOSFET, balance

using the largest area possible to improve Dr MOS

cooling w hile maintaining acceptable noise emission.

3. An output inductor should be located close to the

FDMF6840C to minimize the pow er loss due to the

VSWH copper trace. Care should also be taken so the

inductor dissipation does not heat the DrMOS.

4. Pow erTrench

MOSFETs are used in the output

stage and are effective at minimizing ringing due to

fast sw itching. In most cases, no VSWH snubber is

required. If a snubber is used, it should be placed

close to the VSWH and PGND pins. The selected

resistor and capacitor need to be the proper size for

pow er dissipation.

5. VCIN, VDRV, and BOOT capacitors should be

placed as close as possible to the V CIN-to- CGND,

VDRV-to-CGND, and BOOT-to- PHA SE pin pairs to

ensure clean and stable pow er. Routing w idth and

length should be considered as w ell.

6. Inc lude a trace from the PHASE pin to the VSWH pin

to improve noise margin. Keep this trace as short as

possible.

7. The layout should include the option to insert a

small-value series boot resistor betw een the boot

capacitor

and BOOT

pin.

The

boot-loop size,

including RBOOT and CBOOT, should be as s mall as

possible. The boot resistor may be required w hen

operating above 15 VIN and is effective at controlling

the high-side MOSFET turn-on slew rate and VSHW

overshoot.

RBOOT can improve

noise

operating

margin in synchronous buck designs that may have

noise issues due to ground bounce or high positive

and

negative

VSWH

ringing.

Inserting

boot

resistance low ers the Dr MOS efficiency. Efficiency

versus noise trade-offs must be considered. RBOOT

values from 0.5

Ω to 3.0 Ω are typically effective in

reducing VSWH overshoot.

8. The V IN and PGND pins handle large current

transients w ith frequency components greater than

100 MHz.

possible,

these

pins

should

connected directly to the VIN and board GND

planes. The use of ther mal relief traces in series w ith

these pins is discouraged s ince this adds inductance

to the pow er path. This added inductance in series

w ith either the V IN or PGND pin degrades system

noise immunity by increasing pos itive and negative

VSWH ringing.

9. GND pad and PGND pins should be connected to

the GND copper plane w ith multiple vias for stable

grounding. Poor grounding can create a noise

transient offset voltage level betw een CGND and

PGND. This could lead to faulty operation of the gate

driver and MOSFETs.

10. Ringing

at the BOOT pin

most

effectively

controlled by close placement of the boot capacitor.

Do not add an additional BOOT to the PGND

capacitor. This may lead to excess current flow

through the BOOT diode.

11. The SMOD# and DISB# pins have w eak internal

pull-up and pull-dow n current sources, respectively.

These

pins

should

not

have any

noise filter

capacitors. Do not to float these pins

unless

absolutely necessary.

12. Use multiple vias on the V IN and VOUT copper

areas to interconnect top, inner, and bottom layers

to distribute current flow and heat conduction. Do

not put many vias on the VSWH copper to avoid

extra parasitic

inductance and

noise on the

sw itching w aveform. As long as efficiency and

ther mal perfor mance are acceptable, place only

one VSWH copper on the top layer and use no vias

on the VSWH copper to minimize sw itch node

parasitic noise. Vias should be relatively large and

reasonably

low

inductance.

Cr itical

high-

frequency components, such as RBOOT, CBOOT, RC

snubber, and bypass capacitors; should be located

as close to the respective Dr MOS module pins as

possible on the top layer of the PCB. If this is not

feasible, they can be connected from the backside

through a netw ork of low -inductance vias.

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