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3

Pin Configuration

1

2

3

4

5

6

7

8

9

10

30

29

28

27

26

25

24

23

22

21

VSWH

43

VIN

42

CGND

41

VIN

VIN

VIN

VIN

VSWH

PGND

PGND

PGND

PGND

PGND

PWM

DISB#

THWN#

CGND

GL

VSWH

VSWH

VSWH

VSWH

VSWH

1

2

3

4

5

6

7

8

9

10

30

29

28

27

26

25

24

23

22

21

VSWH

43

VIN

42

CGND

41

VIN

VIN

VIN

VIN

VSWH

PGND

PGND

PGND

PGND

PGND

PWM

DISB#

THWN#

CGND

GL

VSWH

VSWH

VSWH

VSWH

VSWH

Figure 3.

Bottom View

Figure 4.

Top View

Pin Definitions

Pin #

Name

Description

1

SMOD#

When SMOD#=HIGH, the low -side driver is the inverse of the PWM input. When

SMOD#=LOW, the low -side driver is disabled. This pin has a 10 µA internal pull-up current

source. Do not add a noise filter capacitor.

2

VCIN

IC bias supply. Minimum 1 µF ceramic capacitor is recommended from this pin to CGND.

3

VDRV

Pow er for the gate driver. Minimum 1 µF ceramic capacitor is recommended to be connected

as close as possible from this pin to CGND.

4

BOOT

Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a

bootstrap capacitor from this pin to PHASE.

5, 37, 41

CGND

IC ground. Ground return for driver IC.

6

GH

For manufacturing test only. This pin must float; it must not be connected to any pin.

7

PHASE Sw itch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin.

8

NC

No connect. The pin is not electrically connected internally, but can be connected to VIN for

convenience.

9 - 14, 42

VIN

Pow er input. Output stage supply voltage.

15, 29 -

35, 43

VSWH

Sw itch node input. Provides return for high-side bootstrapped driver and acts as a sense point

for the adaptive shoot-through protection.

16 – 28

PGND

Pow er ground. Output stage ground. Source pin of the low -side MOSFET.

36

GL

For manufacturing test only. This pin must float; it must not be connected to any pin.

38

THWN#

Thermal w arning flag, open collector output. When temperature exceeds the trip limit, the

output is pulled LOW. THWN# does not disable the module.

39

DISB#

Output disable. When LOW, this pin disables the pow er MOSFET sw itching (GH and GL are

held LOW). This pin has a 10 µA internal pull-dow n current source. Do not add a noise filter

capacitor.

40

PWM

PWM signal input. This pin accepts a three-state 3.3 V PWM signal from the controller.