EM78P870

8-bit OTP Micro-controller

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* This specification is subject to be changed without notice.

18

8/19/2004 (V1.5)

R9 (PORT9 I/O data, extra LCD address bit)

PAGE0 (PORT9 I/O data register)

7

6

5

4

3

2

1

0

P97

P96

P95

P94

P93

P92

P91

P90

Bit 0 ~ Bit 7 (P90 ~ P97) : 8-bit PORT9(0~7) I/O data register

User can use IOC register to define input or output each bit.

PAGE1 (LCD address MSB bit)

7

6

5

4

3

2

1

0

LCDA8

0

0

0

0

0

0

0

Bit 0 ~ Bit 6 = 0 : unused

Bit 7 (LCDA8) : MSB of LCD address for LCD RAM reading or writing

Other LCD address bits LCDA7 ~ LCDA0 are set from RA PAGE1 Bit 7 ~ Bit 0.

For LCD address access over 0xFFH, set this bit to “1”; otherwise set this bit to “0”.

RA (CPU power saving, PLL, Main clock selection, Watchdog timer, LCD address)

PAGE0 (CPU power saving bit, PLL, Main clock selection bits, Watchdog timer enable bit)

7

6

5

4

3

2

1

0

0

PLLEN

CLK1

CLK0

0

1

1

WDTEN

Bit 0 (WDTEN) : Watch dog control register

User can use WDTC instruction to clear watch dog counter. The counter 's clock source is 32768/2 Hz. If

the prescaler assigns to TCC. Watch dog will time out by (1/32768 )*2 * 256 = 15.616ms. If the prescaler

assigns to WDT, the time of time out will be more times depending on the ratio of prescaler.

0/1

disable/enable

Bit 1~ Bit 2 = 1 : unused

Bit 3 = 0 : unused

Bit 4 ~ Bit 5 (CLK0 ~ CLK1) : Main clock selection bits

User can choose different frequency of main clock by CLK1 and CLK2. All the clock selection is list below.

PLLEN

CLK1

CLK0

Sub clock

MAIN clock

CPU clock

1

0

0

32.768kHz

895.658kHz

895.658kHz (Normal mode)

1

0

1

32.768kHz

1.7913MHz

1.7913MHz (Normal mode)

1

1

0

32.768kHz

10.7479MHz

10.7479MHz (Normal mode)

1

1

1

32.768kHz

3.5826MHz

3.5826MHz (Normal mode)

0

Don’t care

don’t care

32.768kHz

don’t care

32.768kHz (Green mode)

0

Don’t care

don’t care

32.768kHz

don’t care

32.768kHz (Green mode)

0

Don’t care

don’t care

32.768kHz

don’t care

32.768kHz (Green mode)

0

Don’t care

don’t care

32.768kHz

don’t care

32.768kHz (Green mode)

Bit 6 (PLLEN) : PLL enable control bit

It is CPU mode control register. If PLL is enabled, CPU will operate at normal mode (high frequency,main

clock); otherwise, it will run at green mode (low frequency, 32768 Hz).

0/1

disable/enable