EM78P870

8-bit OTP Micro-controller

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* This specification is subject to be changed without notice.

13

8/19/2004 (V1.5)

R3 (Status Register)

7

6

5

4

3

2

1

0

PAGE

IOCP1S

IOCPAGE

T

P

Z

DC

C

Bit 0 (C) : Carry flag

Bit 1 (DC) : Auxiliary carry flag

Bit 2 (Z) : Zero flag

Bit 3 (P) : Power down bit.

Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.

Bit 4 (T) : Time-out bit.

Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout.

EVENT

T

P

REMARK

WDT wake up from sleep mode

0

0

WDT time out (not sleep mode)

0

1

/RESET wake up from sleep

1

0

Power up

1

1

Low pulse on /RESET

x

X

x : don't care

Bit 5(IOCPAGE) : change IOC5 ~ IOCE to another page

Please refer to Fig.4 control register configuration for details.

0/1

page0 / page1

Bit 6(IOCP1S) : change IOC PAGE1 and PAGE2 to another option register

Please refer to Fig.4 control register configuration for details.

0/1

page1 /page2

Bit 6(IOCP1S)

Bit 5 (IOCPAGE)

IOC PAGE SELECT

X

0

PAGE 0

0

1

PAGE 1

1

1

PAGE 2

Bit 7(PAGE) : change R4 ~ RE to another page

Please refer to Fig.4 control register configuration for details.

0/1

page0 / page1

R4 (RAM selection for common registers R20 ~ R3F, SPI control)

PAGE0 (RAM selection register)

7

6

5

4

3

2

1

0

RB1

RB0

RSR5

RSR4

RSR3

RSR2

RSR1

RSR0

Bit 0 ~ Bit 5 (RSR0 ~ RSR5) : Indirect addressing for common registers R20 ~ R3F

RSR bits are used to select up to 32 registers (R20 to R3F) in the indirect addressing mode.

Bit 6 ~ Bit 7 (RB0 ~ RB1) : Bank selection bits for common registers R20 ~ R3F

These selection bits are used to determine which bank is activated among the 4 banks for 32 register (R20 to

R3F)..

Please refer to Fig.4 control register configuration for details.

PAGE1 (SPI control register)

7

6

5

4

3

2

1

0

RBF

SPIE

SRO

SE

SCES

SBR2

SBR1

SBR0

Fig. 6 shows how SPI to communicate with other device by SPI module. If SPI is a master controller, it sends

clock through the SCK pin. An 8-bit data is transmitted and received at the same time. If SPI, however, is

defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be shifted on a