ADL5335

Data Sheet

Rev. 0 | Page 6 of 16

DIGITAL LOGIC TIMING

Table 2.

Parameter

Description

Min

Typ

Max

Unit

Maximum serial clock rate

25

MHz

Minimum period that SCLK is in a logic high state

10

ns

Minimum period that SCLK is in a logic low state

10

ns

Setup time between falling edge of CS and SCLK

15

ns

Hold time between data and rising edge of SCLK

5

ns

Setup time between data and rising edge of SCLK

15

ns

SCLK to SDIO Hold Time

10

ns

Maximum time delay between CS deactivation and SDIO bus to return to high impedance

5

ns

Maximum time delay between falling edge of SCLK and out data valid for a read operation

5

ns

SPI Timing Diagram

CS

SCLK

SDIO

DON’T CARE

DON’T CARE

R/W

A14

A13

A12

A11

A10

A9

D7

D6

D5

D4

D3

D2

D1

D0

DON’T CARE

DON’T CARE

Figure 2. SPI Timing