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LPC802 Scheda tecnica(PDF) 34 Page - NXP Semiconductors |
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LPC802 Scheda tecnica(HTML) 34 Page - NXP Semiconductors |
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34 / 83 page  LPC802 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 1.6 — 27 April 2018 34 of 83 NXP Semiconductors LPC802 32-bit ARM Cortex-M0+ microcontroller 9.23.2 Brownout detection The LPC802 includes one reset level and three interrupt levels for monitoring the voltage on the VDD pin. If this voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a dedicated status register. One threshold level can be selected to cause a forced reset of the chip. Fig 16. Reset pad configuration |
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