LPC802 datasheet(56/83 Pages) NXP

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LPC802

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Product data sheet

Rev. 1.6 — 27 April 2018

56 of 83

NXP Semiconductors

LPC802

32-bit ARM Cortex-M0+ microcontroller

13.7 USART interface

The actual USART bit rate depends on the delays introduced by the external trace, the

external device, system clock (CCLK), and capacitive loading. Excluding delays

introduced by external device and PCB, the maximum supported bit rate for USART

master synchronous mode is 10 Mbit/s, and the maximum supported bit rate for USART

slave synchronous mode is 10 Mbit/s.

Remark: USART functions can be assigned to all digital pins. The characteristics are valid

for all digital pins

Table 22.

USART dynamic characteristics

Tamb = 40 C to 105 C; 1.71 V <= VDD <= 3.6 V unless noted otherwise; CL = 10 pF; input slew = 10 ns. Simulated

parameters sampled at the 30 %/70 % level of the falling or rising edge; values guaranteed by design.

Symbol

Parameter

Conditions

Min

Max

Unit

USART master (in synchronous mode)

tsu(D)

data input set-up time

3.0 V <= VDD <= 3.6 V

1.71 V <= VDD < 3.0 V

th(D)

data input hold time

3.0 V <= VDD <= 3.6 V

1.71 V <= VDD < 3.0 V

tv(Q)

data output valid time

3.0 V <= VDD <= 3.6 V

1.71 V <= VDD < 3.0 V

USART slave (in synchronous mode)

tsu(D)

data input set-up time

3.0 V <= VDD <= 3.6 V

1.71 V <= VDD < 3.0 V

th(D)

data input hold time

3.0 V <= VDD <= 3.6 V

1.71 V <= VDD < 3.0 V

tv(Q)

data output valid time

3.0 V <= VDD <= 3.6 V

1.71 V <= VDD < 3.0 V

Fig 29. USART timing

Un_SCLK (CLKPOL = 0)

TXD

RXD

Tcy(clk)

tsu(D) th(D)

tv(Q)

START

BIT0

tvQ)

Un_SCLK (CLKPOL = 1)

START

BIT0

BIT1

aaa-015074

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