IR2114SS datasheet(13/21 Pages) IRF

13 / 21 page

IR2114/IR21141/IR2214/IR22141

tBL

Blanking

VB/Vcc

HONH/L

DSH/L

VS/COM

HOPH/L

tss

One Shot

VDESAT

(ton1)

ONE

SHOT

tDS

filter

SSDH/L

Prre

Drriivve

err

sensing

diode

on/off

DesatHS/LS

desat

comparator

Figure 13: high and low side output stage

FLTCLR

SET

CLR

FAULT/SD

SY_FLT

internal

HOLD

(external

hold)

(external hard

shutdown)

internal FAULT

(hard shutdown)

UVCC

DesatHS

DesatLS

Figure 14: fault management diagram

The external sensing diode should have BV>600V

or 1200V and low stray capacitance (in order to

minimize noise coupling and switching delays).

The diode is biased by an internal pull-up resistor

RDSH/L (equal to VCC/IDS- or VBS/IDS- for IR2114 or

IR2214) or by a dedicated circuit (see the active-

bias section for IR21141 and IR22141). When VCE

increases, the voltage at DSH/L pin increases too.

Being internally biased to the local supply, DSH/L

voltage is automatically clamped. When DSH/L

exceeds the VDESAT+ threshold the comparator

triggers (see figure 13). Comparator output is

filtered in order to avoid false desaturation

detection by externally induced noise; pulses

shorter than tDS are filtered out. To avoid detecting

a false desaturation during IGBT turn on, the

desaturation circuit is disabled by a Blanking signal

(TBL, see Blanking block in figure 13). This time is

the estimated maximum IGBT turn on time and

must be not exceeded by proper gate resistance

sizing. When the IGBT is not completely saturated

after TBL, desaturation is detected and the driver

will turn off.

Eligible desaturation signals initiate the Soft

Shutdown sequence (SSD). While in SSD, the

output driver goes in high impedance and the SSD

pull-down is activated to turn off the IGBT through

SSDH/L pin. The SY_FLT output pin (active low,

see figure 14) reports the gate driver status all the

way long SSD sequence lasts (tSS). Once finished

SSD, SYS_FLT releases, and the gate driver

generates a FAULT signal (see the FAULT/SD

section) by

activating FAULT/SD pin.

This

generates a hard shut down for both high and low

output stages (HO=LO=low). Each driver is latched

low until the fault is cleared (see FLT_CLR).

Figure 14 shows the fault management circuit. In

this diagram DesatHS and DesatLS are two

internal signals that come from the output stages

(see figure 13).

It must be noted that while in Soft Shut Down, both

Under Voltage fault and external Shut Down (SD)

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