AD5669RBCBZ-1-R5 datasheet(26/30 Pages) AD

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AD5629R/AD5669R

Data Sheet

Rev. F | Page 26 of 30

POWER-DOWN MODES

The AD5629R/AD5669R contain four separate modes of

operation. Command 0100 is reserved for the power-down

function (see Table 8). These modes are software-programmable

by setting two bits, Bit DB9 and Bit DB8, in the control register.

Table 12 shows how the state of the bits corresponds to the

mode of operation of the device. Any or all DACs (DAC H to

DAC A) can be powered down to the selected mode by setting

the corresponding eight bits (DB7 to DB0) to 1. See Table 13 for

the contents of the input shift register during power-down/power-

up operation.

When both bits are set to 0, the part works normally with its

normal power consumption of 1.3 mA at 5 V. However, for the

three power-down modes, the supply current falls to 0.4 µA at

5 V (0.2 µA at 3 V). Not only does the supply current fall, but

the output stage is also internally switched from the output of

the amplifier to a resistor network of known values. This has the

advantage that the output impedance of the part is known while

the part is in power-down mode. There are three different

options. The output is connected internally to GND through

either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited

(three-state). The output stage is illustrated in Figure 55.

RESISTOR

NETWORK

VOUT

RESISTOR

STRING DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

Figure 55. Output Stage During Power-Down

The bias generator of the selected DAC(s), output amplifier,

resistor string, and other associated linear circuitry is shut down

when the power-down mode is activated. The internal reference

is powered down only when all channels are powered down.

However, the contents of the DAC register are unaffected when

in power-down. The time to exit power-down is typically 4 µs

for VDD = 5 V and for VDD = 3 V.

Any combination of DACs can be powered up by setting PD1

and PD0 to 0 (normal operation). The output powers up to the

value in the input register (LDAC low) or to the value in the

DAC register before powering down (LDAC high).

CLEAR CODE REGISTER

The AD5629R/AD5669R have a hardware CLR pin that is an

asynchronous clear input. The CLR input is falling edge sensitive.

Bringing the CLR line low clears the contents of the input

configurable CLR register and sets the analog outputs accordingly.

This function can be used in system calibration to load zero scale,

midscale, or full scale to all channels together. These clear code

values are user-programmable by setting two bits, Bit DB1 and

Bit DB0, in the CLR control register (see Table 15). The default

setting clears the outputs to 0 V. Command 0101 is reserved for

loading the clear code register (see Table 8).

The part exits clear code mode at the end of the next valid write

to the part. If CLR is activated during a write sequence, the write

is aborted.

The CLR pulse activation time (the falling edge of CLR to when

the output starts to change) is typically 280 ns. However, if

outside the DAC linear region, it typically takes 520 ns after

executing CLR for the output to start changing (see Figure 44).

See Table 14 for the contents of the input shift register during

the loading clear code register operation.

Table 10. Internal Reference Register

Internal REF Register (DB0)

Action

Reference off (default)

Reference on

Table 11. 32-Bit Input Shift Register Contents for Reference Set-Up Command

MSB

LSB

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15 to DB1

DB0

1/0

Command bits (C3 to C0)

Address bits (A3 to A0)—don’t cares

Don’t cares

Internal REF on/off

Table 12. Power-Down Modes of Operation

DB9

DB8

Operating Mode

Normal operation

Power-down modes

1 kΩ to GND

100 kΩ to GND

Three-state

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