AD5669RBCBZ-1-R5 datasheet(11/30 Pages) AD

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Data Sheet

AD5629R/AD5669R

Rev. F | Page 11 of 30

Table 6. Pin Function Descriptions

Pin No.

LFCSP

TSSOP

WLCSP

Mnemonic

Description

LDAC

Pulsing this pin low allows any or all DAC registers to be updated if the input registers

have new data. This allows all DAC outputs to simultaneously update. Alternatively,

this pin can be tied permanently low.

Address Input. Sets the least significant bit of the 7-bit slave address.

VDD

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. Decouple the

supply with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

VOUTA

Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

VOUTC

Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

VOUTE

Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.

VOUTG

Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.

VREFIN/VREFOUT

The AD5629R/AD5669R have a common pin for reference input and reference output.

When using the internal reference, this is the reference output pin. When using an

external reference, this is the reference input pin. The default for this pin is as a

reference input.

CLR

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all

LDAC pulses are ignored. When CLR is activated, the input register and the DAC

midscale, or full scale. The default setting clears the output to 0 V.

VOUTH

Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.

VOUTF

Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.

VOUTD

Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

VOUTB

Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

GND

Ground Reference Point for All Circuitry on the Parts.

SDA

Serial Data Input. This is used in conjunction with the SCL line to clock data into or

out of the 32-bit input shift register. It is a bidirectional, open-drain data line that

should be pulled to the supply with an external pull-up resistor.

SCL

Serial Clock Line. This is used in conjunction with the SDA line to clock data into or

out of the 32-bit input shift register.

N/A

Exposed Pad

(EPAD)

The exposed pad must be tied to GND.

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