MB90335 datasheet(30/84 Pages) FUJI

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MB90335 Series

Watchdog timer

• The watchdog timer is a timer counter prepared in case programs run out of control.

• The watchdog timer is a 2-bit counter using the time-base timer as the count clock.

• When started, the watchdog timer resets the CPU if it is not cleared before the two-bit counter overflows.

•••• Interval time of watchdog timer

Notes :

• The maximum and minimum time intervals for the watchdog timer depend on the counter clear timing.

• The watchdog timer contains a 2-bit counter that counts the carry signals of the time-base timer. When

the device is operating with HCLK, therefore, clearing the time-base timer lengthens the watchdog reset

generation time interval.

• Event that stop the watchdog timer

1 : Stop due to a Power-on reset

2 : watchdog reset

• Clear factor of watch dog timer

1 : External reset input by RST pin

2 : Writing “0” to the software reset bit

3 : Writing “0” to the watchdog control bit (second and subsequent times)

4 : Transition to sleep mode (Clearing the watchdog timer, and suspend counting)

5 : Transition to time-base timer mode (Clearing the watchdog timer, and suspend counting)

6 : Transition to stop mode (Clearing the watchdog timer, and suspend counting)

• Register list

HCLK: Oscillation clock (6 MHz)

Min

Max

Clock cycle

Approx. 2.39 ms

Approx. 3.07 ms

214

± 211 / HCLK

Approx. 9.56 ms

Approx. 12.29 ms

216

± 213 / HCLK

Approx. 38.23 ms

Approx. 49.15 ms

218

± 215 / HCLK

Approx. 305.83 ms

Approx. 393.22 ms

221

± 218 / HCLK

Watchdog timer control register (WDTC)

Initial Value

Address : 0000A8H

X-XXX111B

(

 )

( R )

( W )

( R )

PONR

WRST

ERST

SRST

WTE

WT1

WT0



Preliminary

2004.01.09

MB90335 Scheda tecnica(PDF) 30 Page - Fuji Electric

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