NT5CB128M8GP-EKB datasheet(100/160 Pages) NANYA

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Version 2.2

100

Nanya Technology Cooperation ©

04/2019

NTC Proprietary

Level: Property

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross

point voltage of differential input signals (CK,

 and DQS, ) must meet the requirements in the following table. The

differential input cross point voltage Vix is measured from the actual cross point of true and complete signal to the midlevel

between of VDD and VSS.

Vix Definition

VDD

VSS

VDD/2

,

CK,DQS

VIX

VSEL

Cross point voltage for differential input signals (CK, DQS)

Symbol

Parameter

DDR3

DDR3L

Unit

Notes

800/1066/1333/1600/

1866/2133

1066/1333/1600/

1866

Min

Max

Min

Max

VIX(CK)

Differential Input Cross Point

Voltage relative to

VDD/2 for CK,



- 150

+ 150

- 150

+ 150

- 175

+ 175

VIX(DQS)

Differential Input Cross Point

Voltage relative to

VDD/2 for DQS,



- 150

+ 150

- 150

+ 150

Note 1

The relation between Vix Min/Max and VSEL/VSEH should satisfy following:

(VDD/2) + VIX (min) - VSEL >= 25 mV ;

VSEH - ((VDD/2) + VIX (max)) >= 25 mV;

Note 2

Extended range for Vix is only allowed for clock and if single-ended clock input signals CK and

 are monotonic with a

single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK -

 is larger

than 3 V/ns.

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