XIO2000AI datasheet(38/160 Pages) TI1

38 / 160 page

Feature/Protocol Descriptions

April 2007 Revised October 2008

SCPS155C

Table 3−3. Messages Supported by the Bridge

MESSAGE

SUPPORTED

BRIDGE ACTION

Assert_INTx

Yes

Transmitted upstream

Deassert_INTx

Yes

Transmitted upstream

PM_Active_State_Nak

Yes

Received and processed

PM_PME

Yes

Transmitted upstream

PME_Turn_Off

Yes

Received and processed

PME_TO_Ack

Yes

Transmitted upstream

ERR_COR

Yes

Transmitted upstream

ERR_NONFATAL

Yes

Transmitted upstream

ERR_FATAL

Yes

Transmitted upstream

Unlock

Yes

Received and processed

Set_Slot_Power_Limit

Yes

Received and processed

Hot plug messages

Discarded

Advanced switching messages

Discarded

Vendor defined type 0

Unsupported request

Vendor defined type 1

Discarded

All supported message transactions are processed per the PCI Express Base Specification.

3.4

PCI Bus Interface

3.4.1 I/O Characteristics

Figure 3−4 shows a 3-state bi-directional buffer that represents the I/O cell design for the PCI bus. Section

7.7, Electrical Characteristics over Recommended Operating Conditions, provides the electrical

characteristics of the PCI bus I/O cell.

NOTE: The PCI bus interface on the bridge meets the ac specifications of the PCI Local Bus

Specification. Additionally, PCI bus terminals (input or I/O) must be held high or low to prevent

them from floating.

Tied for Open Drain

Pad

VCCP

Figure 3−4. 3-State Bidirectional Buffer

3.4.2 Clamping Voltage

In the bridge, the PCI bus I/O drivers are powered from the VDD_33 power rail. Plus, the I/O driver cell is tolerant

to input signals with 5.0-V peak-to-peak amplitudes.

For PCI bus interfaces operating at 66 MHz, all devices are required to output only 3.3-V peak-to-peak signal

amplitudes. For PCI bus interfaces operating at 33-MHz, devices may output either 3.3-V or 5.0-V

peak-to-peak signal amplitudes. The bridge accommodates both signal amplitudes.

Each PCI bus I/O driver cell has a clamping diode connected to the VCCP voltage rail that protects the cell

from excessive input voltage. If the PCI signaling is 3.3-V, then VCCP (A04, J01) is connected to a 3.3-V power

supply. If the PCI signaling is 5.0 V, then VCCP (A04, J01) is connected to a 5.0-V power supply.

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