XIO2000AI datasheet(89/160 Pages) TI1

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Classic PCI Configuration Space

April 2007 Revised October 2008

SCPS155C

4.60 GPIO Data Register

This register reads the state of the input mode GPIO terminals and changes the state of the output mode GPIO

terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The secondary

functions share GPIO0 (CLKRUN), GPIO1 (PWR_OVRD), GPIO4 (SCL), and GPIO5 (SDA). The default

value at power up depends on the state of the GPIO terminals as they default to general-purpose inputs. See

Table 4−34 for a complete description of the register contents.

PCI register offset:

B6h

Read-only, Read/Write

Default value:

00XXh

BIT NUMBER

RESET STATE

Table 4−34. GPIO Data Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:8

RSVD

Reserved. Returns 00h when read.

7†

GPIO7_DATA

GPIO 7 data. This bit reads the state of GPIO7 when in input mode or changes the state of GPIO7

when in output mode.

6†

GPIO6_DATA

GPIO 6 data. This bit reads the state of GPIO6 when in input mode or changes the state of GPIO6

when in output mode.

5†

GPIO5_DATA

GPIO 5 data. This bit reads the state of GPIO5 when in input mode or changes the state of GPIO5

when in output mode.

4†

GPIO4_DATA

GPIO 4 data. This bit reads the state of GPIO4 when in input mode or changes the state of GPIO4

when in output mode.

3†

GPIO3_DATA

GPIO 3 data. This bit reads the state of GPIO3 when in input mode or changes the state of GPIO3

when in output mode.

2†

GPIO2_DATA

GPIO 2 data. This bit reads the state of GPIO2 when in input mode or changes the state of GPIO2

when in output mode.

1†

GPIO1_DATA

GPIO 1 data. This bit reads the state of GPIO1 when in input mode or changes the state of GPIO1

when in output mode.

0†

GPIO0_DATA

GPIO 0 data. This bit reads the state of GPIO0 when in input mode or changes the state of GPIO0

when in output mode.

† These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

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