| Motore di ricerca datesheet componenti elettronici |
|
GD25Q64CFJS Scheda tecnica(PDF) 34 Page - GigaDevice Semiconductor (Beijing) Inc. |
|
|
|||||||||||||||||||||||||||||
GD25Q64CFJS Scheda tecnica(HTML) 34 Page - GigaDevice Semiconductor (Beijing) Inc. |
|
34 / 74 page ![]() 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q64C 34 7.22. Release from Deep Power-Down or High Performance Mode and Read Device ID (RDI) (ABH) The Release from Power-Down or High Performance Mode / Device ID command is a multi-purpose command. It can be used to release the device from the Power-Down state or High Performance Mode or obtain the devices electronic identification (ID) number. To release the device from the Power-Down state or High Performance Mode, the command is issued by driving the CS# pin low, shifting the instruction code “ABH” and driving CS# high as shown in Figure26. Release from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other c omma nd are accepted. The CS# pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the Power-Down state, the command is initiated by driving the CS# pin low and shifting the instruction code “ABH” followed by 3-dummy byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure27. The Device ID value is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The command is completed by driving CS# high. When used to release the device from the Power-Down state and obtain the Device ID, the command is the same as previously described, and shown in Figure27, except that after CS# is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other command will be accepted. If the Release from Power-Down / Device ID command is issued while an Erase, Program or Write cycle is in process (when WIP equal 1) the command is ignored and will not have any effects on the current cycle. Figure 26. Release Power-Down Sequence or High Performance Mode Sequence Diagram Figure 27. Release Power-Down/Read Device ID Sequence Diagram Command 0 1 2 3 4 5 6 7 ABH CS# SCLK SI RES1 Stand-by mode Deep Power-down mode t Command 0 1 2 3 4 5 6 7 ABH CS# SCLK SI 8 9 29 30 31 MSB 2 1 0 3 Dummy Bytes 23 22 32 33 34 35 36 37 38 7 6 5 4 3 2 1 0 SO MSB t RES2 Stand-by Mode Deep Power-down Mode High-Z Device ID |
|
Link URL |
| Lei ha avuto il aiuto da alldatasheet? [ DONATE ] |
Di alldatasheet | Richest di pubblicita | contatti | Privacy Policy | Collegamento alla scheda tecnica | scambio Link | Ricerca produttore All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |