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GD25VQ127CSFS Scheda tecnica(PDF) 9 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25VQ127CSFS Scheda tecnica(HTML) 9 Page - GigaDevice Semiconductor (Beijing) Inc. |
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9 / 62 page ![]() Uniform Sector Dual and Quad Serial Flash GD25VQ127C 9 RESET The RESET# pin allows the device to be reset by the control. For the WSON8 package, the pin7 can be configured as a RESET# pin depending on the status register setting, which need QE=0 and HOLD/RST=1. On the SOP16 package, a dedicated RESET# pin is provided and it is independent of QE bit setting. The RESET# pin goes low for a period of tRLRH or longer will reset the flash. After reset cycle, the flash is at the following states: -Standby mode -All the volatile bits will return to the default status as power on. Figure2. RESET Condition CS# RESET# RESET |
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