P89C60X2BASLASH00 datasheet(42/56 Pages) PHILIPS

42 / 56 page

Philips Semiconductors

Product data

P89C60X2/61X2

80C51 8-bit Flash microcontroller family

64KB Flash, 512B/1024B RAM

2003 Sep 11

An interrupt will be serviced as long as an interrupt of equal or

higher priority is not already being serviced. If an interrupt of equal

or higher level priority is being serviced, the new interrupt will wait

until it is finished before being serviced. If a lower priority level

interrupt is being serviced, it will be stopped and the new interrupt

serviced. When the new interrupt is finished, the lower priority level

interrupt that was stopped will be completed.

Table 10.

Interrupt Table

SOURCE

POLLING PRIORITY

REQUEST BITS

HARDWARE CLEAR?

VECTOR ADDRESS

External interrupt 0

IE0

N (L)1

Y (T)2

03H

Timer 0

TF0

0BH

External interrupt 1

IE1

N (L)

Y (T)

13H

Timer 1

TF1

1BH

UART

RI, TI

23H

Timer 2

TF2, EXF2

2BH

NOTES:

1. L = Level activated

2. T = Transition activated

Reduced EMI Mode

The AO bit (AUXR.0) in the AUXR register when set disables the

ALE output, unless the CPU needs to perform an off-chip memory

access.

AUXR (8EH)

–

EXTRAM

AUXR.0

Turns off ALE output.

AUXR.1

EXTRAM

Controls external data memory

access.

Dual DPTR

The dual DPTR structure (see Figure 28) enables a way to specify

the address of an external data memory location. There are two

16-bit DPTR registers that address the external memory, and a

single bit called DPS = AUXR1/bit0 that allows the program code to

switch between them.

• New Register Name: AUXR1#

• SFR Address: A2H

• Reset Value: xxx000x0B

AUXR1 (A2H)

–

GF2

–

DPS

Where:

DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.

Select Reg

DPS

DPTR0

DPTR1

The DPS bit status should be saved by software when switching

between DPTR0 and DPTR1.

The GF2 bit is a general purpose user-defined flag.

Note that bit 2 is not writable and is always read as a zero. This

allows the DPS bit to be quickly toggled simply by executing an INC

AUXR1 instruction without affecting the GF2 bit.

DPS

DPTR1

DPTR0

DPH

(83H)

DPL

(82H)

EXTERNAL

DATA

MEMORY

SU00745A

BIT0

AUXR1

Figure 28.

DPTR Instructions

The instructions that refer to DPTR refer to the data pointer that is

currently selected using the AUXR1/bit 0 register. The six

instructions that use the DPTR are as follows:

INC DPTR

Increments the data pointer by 1

MOV DPTR, #data16

Loads the DPTR with a 16-bit constant

MOV A, @ A+DPTR

Move code byte relative to DPTR to ACC

MOVX A, @ DPTR

Move external RAM (16-bit address) to

ACC

MOVX @ DPTR , A

Move ACC to external RAM (16-bit

address)

JMP @ A + DPTR

Jump indirect relative to DPTR

The data pointer can be accessed on a byte-by-byte basis by

specifying the low or high byte in an instruction which accesses the

SFRs. See application note AN458 for more details.

P89C60X2BA/00 Scheda tecnica(PDF) 42 Page - NXP Semiconductors

P89C60X2BA/00 Scheda tecnica(HTML) 42 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Scheda tecnica Scarica

Link URL