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P89C60X2BA/00 Scheda tecnica(PDF) 47 Page - NXP Semiconductors |
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P89C60X2BA/00 Scheda tecnica(HTML) 47 Page - NXP Semiconductors |
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47 / 56 page  Philips Semiconductors Product data P89C60X2/61X2 80C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM 2003 Sep 11 47 AC ELECTRICAL CHARACTERISTICS (12-CLOCK MODE) Tamb = 0 °C to +70 °C; VCC = 5 V ± 10%, VSS = 0 V1, 2, 3 SYMBOL FIGURE PARAMETER VARIABLE CLOCK4 33 MHz CLOCK4 MIN MAX MIN MAX UNIT 1/tCLCL 35 Oscillator frequency 0 33 MHz tLHLL 31 ALE pulse width 2tCLCL–40 21 ns tAVLL 31 Address valid to ALE low tCLCL–25 5 ns tLLAX 31 Address hold after ALE low tCLCL–25 5 ns tLLIV 31 ALE low to valid instruction in 4tCLCL–65 55 ns tLLPL 31 ALE low to PSEN low tCLCL–25 5 ns tPLPH 31 PSEN pulse width 3tCLCL–45 45 ns tPLIV 31 PSEN low to valid instruction in 3tCLCL–60 30 ns tPXIX 31 Input instruction hold after PSEN 0 0 ns tPXIZ 31 Input instruction float after PSEN tCLCL–25 5 ns tAVIV 31 Address to valid instruction in 5tCLCL–80 70 ns tPLAZ 31 PSEN low to address float 10 10 ns Data Memory tRLRH 32 RD pulse width 6tCLCL–100 82 ns tWLWH 33 WR pulse width 6tCLCL–100 82 ns tRLDV 32 RD low to valid data in 5tCLCL–90 60 ns tRHDX 32 Data hold after RD 0 0 ns tRHDZ 32 Data float after RD 2tCLCL–28 32 ns tLLDV 32 ALE low to valid data in 8tCLCL–150 90 ns tAVDV 32 Address to valid data in 9tCLCL–165 105 ns tLLWL 32, 33 ALE low to RD or WR low 3tCLCL–50 3tCLCL+50 40 140 ns tAVWL 32, 33 Address valid to WR low or RD low 4tCLCL–75 45 ns tQVWX 33 Data valid to WR transition tCLCL–30 0 ns tWHQX 33 Data hold after WR tCLCL–25 5 ns tQVWH 33 Data valid to WR high 7tCLCL–130 80 ns tRLAZ 32 RD low to address float 0 0 ns tWHLH 32, 33 RD or WR high to ALE high tCLCL–25 tCLCL+25 5 55 ns External Clock tCHCX 35 High time 17 tCLCL–tCLCX ns tCLCX 35 Low time 17 tCLCL–tCHCX ns tCLCH 35 Rise time 5 ns tCHCL 35 Fall time 5 ns Shift Register tXLXL 34 Serial port clock cycle time 12tCLCL 360 ns tQVXH 34 Output data setup to clock rising edge 10tCLCL–133 167 ns tXHQX 34 Output data hold after clock rising edge 2tCLCL–80 50 ns tXHDX 34 Input data hold after clock rising edge 0 0 ns tXHDV 34 Clock rising edge to input data valid 10tCLCL–133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are tested to 3.5 MHz, but guaranteed to operate down to 0 Hz. |
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