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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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P89C60X2BA/00 Scheda tecnica(PDF) 48 Page - NXP Semiconductors |
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P89C60X2BA/00 Scheda tecnica(HTML) 48 Page - NXP Semiconductors |
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48 / 56 page  Philips Semiconductors Product data P89C60X2/61X2 80C51 8-bit Flash microcontroller family 64KB Flash, 512B/1024B RAM 2003 Sep 11 48 AC ELECTRICAL CHARACTERISTICS (6-CLOCK MODE) Tamb = 0 °C to +70 °C; VCC = 5 V ± 10%, VSS = 0 V1, 2, 3 SYMBOL FIGURE PARAMETER VARIABLE CLOCK4 20 MHz CLOCK4 MIN MAX MIN MAX UNIT 1/tCLCL 35 Oscillator frequency 0 20 MHz tLHLL 31 ALE pulse width tCLCL–40 10 ns tAVLL 31 Address valid to ALE low 0.5tCLCL–20 5 ns tLLAX 31 Address hold after ALE low 0.5tCLCL–20 5 ns tLLIV 31 ALE low to valid instruction in 2tCLCL–65 35 ns tLLPL 31 ALE low to PSEN low 0.5tCLCL–20 5 ns tPLPH 31 PSEN pulse width 1.5tCLCL–45 30 ns tPLIV 31 PSEN low to valid instruction in 1.5tCLCL–60 15 ns tPXIX 31 Input instruction hold after PSEN 0 0 ns tPXIZ 31 Input instruction float after PSEN 0.5tCLCL–20 5 ns tAVIV 31 Address to valid instruction in 2.5tCLCL–80 45 ns tPLAZ 31 PSEN low to address float 10 10 ns Data Memory tRLRH 32 RD pulse width 3tCLCL–100 50 ns tWLWH 33 WR pulse width 3tCLCL–100 50 ns tRLDV 32 RD low to valid data in 2.5tCLCL–90 35 ns tRHDX 32 Data hold after RD 0 0 ns tRHDZ 32 Data float after RD tCLCL–20 5 ns tLLDV 32 ALE low to valid data in 4tCLCL–150 50 ns tAVDV 32 Address to valid data in 4.5tCLCL–165 60 ns tLLWL 32, 33 ALE low to RD or WR low 1.5tCLCL–50 1.5tCLCL+50 25 125 ns tAVWL 32, 33 Address valid to WR low or RD low 2tCLCL–75 25 ns tQVWX 33 Data valid to WR transition 0.5tCLCL–25 0 ns tWHQX 33 Data hold after WR 0.5tCLCL–20 5 ns tQVWH 33 Data valid to WR high 3.5tCLCL–130 45 ns tRLAZ 32 RD low to address float 0 0 ns tWHLH 32, 33 RD or WR high to ALE high 0.5tCLCL–20 0.5tCLCL+20 5 45 ns External Clock tCHCX 35 High time 20 tCLCL–tCLCX ns tCLCX 35 Low time 20 tCLCL–tCHCX ns tCLCH 35 Rise time 5 ns tCHCL 35 Fall time 5 ns Shift Register tXLXL 34 Serial port clock cycle time 6tCLCL 300 ns tQVXH 34 Output data setup to clock rising edge 5tCLCL–133 117 ns tXHQX 34 Output data hold after clock rising edge tCLCL–30 20 ns tXHDX 34 Input data hold after clock rising edge 0 0 ns tXHDV 34 Clock rising edge to input data valid 5tCLCL–133 117 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. |
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