EP9315 datasheet(36/64 Pages) CIRRUS

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DS638PP4

EP9315

Enhanced Universal Platform SOC Processor

Ultra DMA Data Transfer

Figure 21 through Figure 30 define the timings associated with all phases of Ultra DMA bursts. The following table

contains the values for the timings for each of the Ultra DMA modes.

Note:

1. Timing parameters shall be measured at the connector of the sender or receiver to which the parameter applies.

2. The test load for tDVS and tDVH shall be a lumped capacitor load with no cable or receivers. Timing for tDVS and tDVH shall be

met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value.

3. tUI, tMLI and tLI indicate sender-to-recipient or recipient-to-sender interlocks, i.e., either sender or recipient is waiting for the

other to respond with a signal before proceeding. tUI is an unlimited interlock that has no maximum time value. tMLI is a limited

time-out that has a defined minimum. tLI is a limited time-out that has a defined maximum.

4. tZIORDY may be greater than tENV since the device has a pull up on IORDYn giving it a known state when released.

5. All IDE timing is based upon HCLK = 100 MHz.

Timing reference levels = 1.5 V

Parameter

Symbol

Mode 0

(in ns)

Mode 1

(in ns)

Mode 2

(in ns)

Mode 3

(in ns)

min

max

min

max

min

max

min

max

Cycle time allowing for asymmetry and clock variations

(from DSTROBE edge to DSTROBE edge)

tCYCRD

112

Two-cycle time allowing for clock variations (from rising edge to next

rising edge or from falling edge to next falling edge of DSTROBE)

t2CYCRD

230

154

115

Cycle time allowing for asymmetry and clock variations

(from HSTROBE edge to HSTROBE edge)

tCYCWR

230

170

130

100

Two-cycle time allowing for clock variations (from rising edge to next

rising edge or from falling edge to next falling edge of HSTROBE)

t2CYCWR

460

340

260

200

Data setup time at recipient (Read)

tDS

7-7-

Data hold time at recipient (Read)

tDH

8-8

8-8-

Data valid setup time at sender (Write)

(Note 2)

(from data valid until STROBE edge)

tDVS

Data valid hold time at sender (Write)

(Note 2)

(from STROBE edge until data may become invalid)

tDVH

6-6

6-6-

First STROBE time (for device to first negate DSTROBE from STOP

during a data in burst)

tFS

230

200

170

130

Limited interlock time

(Note 3)

tLI

150

100

Interlock time with minimum

(Note 3)

tMLI

Unlimited interlock time

(Note 3)

tUI

0-0

0-0-

Maximum time allowed for output drivers to release

(from asserted or negated)

tAZ

-10-10

Minimum delay time required for output

tZAH

Drivers to assert or negate (from released)

tZAD

0-0

0-0-

Envelope time (from DMACKn to STOP and HDMARDYn during data in

burst initiation and from DMACKn to STOP during data out burst initiation)

tENV

Ready-to-final-STROBE time (no STROBE edges shall be sent this long

after negation of DMARDYn)

tRFS

-75-70

-60-60

Ready-to-pause time

(that recipient shall wait to pause after negating DMARDYn)

tRP

160

125

100

Maximum time before releasing IORDY

tIORDYZ

-20-20

Minimum time before driving STROBE

(Note 4)

tZIORDY

0-0

0-0-

Setup and hold times for DMACKn (before assertion or negation)

tACK

Time from STROBE edge to negation of DMARQ or assertion of STOP

(when sender terminates a burst)

tSS

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