M58LT128GST datasheet(8/98 Pages) STMICROELECTRONICS

8 / 98 page

1 Summary description

M58LT128GST, M58LT128GSB

8/98

Summary description

The M58LT128GST and M58LT128GSB are 128 Mbit (8 Mbit x16) non-volatile Secure Flash

memories.

The devices may be erased electrically at block level and programmed in-system on a Word-by-

Word basis using a 1.7 to 2.0V VDD supply for the circuitry and a 2.7 to 3.6V VDDQ supply for

the Input/Output pins. An optional 9V VPP power supply is provided to speed up factory

programming.

The devices feature an asymmetrical block architecture and are based on a multi-level cell

technology. The memory array is organized as 131 blocks, and is divided into 8 Mbit banks.

There are 15 banks each containing 8 main blocks of 64 KWords, and one parameter bank

containing 4 parameter blocks of 16 KWords and 7 main blocks of 64 KWords.

The Multiple Bank Architecture allows Dual Operations, while programming or erasing in one

bank, read operations are possible in other banks. Only one bank at a time is allowed to be in

program or erase mode. It is possible to perform burst reads that cross bank boundaries. The

bank architecture is summarized in Table 2, and the memory maps are shown in Figure 3. The

Parameter Blocks are located at the top of the memory address space for the M58LT128GST,

and at the bottom for the M58LT128GSB.

Each block can be erased separately. Erase can be suspended, in order to perform a program

or read operation in any other block, and then resumed. Program can be suspended to read

data at any memory location except for the one being programmed, and then resumed. Each

block can be programmed and erased over 100,000 cycles using the supply voltage VDD. There

is a Buffer Enhanced Factory programming command available to speed up programming.

Program and erase commands are written to the Command Interface of the memory. An

internal Program/Erase Controller takes care of the timings necessary for program and erase

operations. The end of a program or erase operation can be detected and any error conditions

identified in the Status Register. The command set required to control the memory is consistent

with JEDEC standards.

The device supports Synchronous Burst Read and Asynchronous Read and Page Read from

all blocks of the memory array; at power-up the device is configured for Asynchronous Read. In

Synchronous Burst Read mode, data is output on each clock cycle at frequencies of up to

52MHz. The Synchronous Burst Read operation can be suspended and resumed.

The device features an Automatic Standby mode. When the bus is inactive during

Asynchronous Read operations, the device automatically switches to the Automatic Standby

mode. In this condition the power consumption is reduced to the standby value and the outputs

are still driven.

The M58LT128GST and M58LT128GSB are equipped with several features to increase data

protection:

●

Hardware Protection: all blocks are protected from program and erase operations when

the VPP ≤VPPLK .

●

A full set of Software Security Features described in a dedicated Application Note. Please

contact STMicroelectronics for further details.

●

64-bit Unique Device Identifier

●

2112 bits of User-Programmable OTP memory

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