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DRV8426PWPR Scheda tecnica(PDF) 40 Page - Texas Instruments |
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DRV8426PWPR Scheda tecnica(HTML) 40 Page - Texas Instruments |
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40 / 49 page ![]() www.ti.com EXAMPLE BOARD LAYOUT 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND 24X (0.25) 24X (0.6) ( 0.2) TYP VIA 20X (0.5) (3.8) (3.8) ( 2.45) (R0.05) TYP (0.975) TYP VQFN - 1 mm max height RGE0024B PLASTIC QUAD FLATPACK - NO LEAD 4219013/A 05/2017 SYMM 1 6 7 12 13 18 19 24 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 25 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DETAILS DEFINED (PREFERRED) EXPOSED METAL 40 DRV8426 SLOSE55 – MAY 2020 www.ti.com Product Folder Links: DRV8426 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated |
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