PIC24H datasheet(114/290 Pages) MICROCHIP

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PIC24H

DS70175D-page 114

Preliminary

FIGURE 7-1:

TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS

7.1

DMAC Registers

Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7)

contains the following registers:

• A 16-bit DMA Channel Control register

(DMAxCON)

• A 16-bit DMA Channel IRQ Select register

(DMAxREQ)

• A 16-bit DMA RAM Primary Start Address register

(DMAxSTA)

• A 16-bit DMA RAM Secondary Start Address

• A 16-bit DMA Peripheral Address register

(DMAxPAD)

• A 10-bit DMA Transfer Count register (DMAx-

CNT)

An additional status register, DMACS, is common to

all DMAC channels. It contains the DMA RAM and

SFR write collision flags, XWCOLx and PWCOLx,

respectively.

The

DMAxCON,

DMAxREQ,

DMAxPAD

and

DMAxCNT are all conventional read/write registers.

Reads of DMAxSTA or DMAxSTB will read the con-

tents of the DMA RAM Address register. Writes to

DMAxSTA or DMAxSTB write to the registers. This

allows the user to determine the DMA buffer pointer

value (address) at any time.

The interrupt flags (DMAxIF) are located in an IFSx

interrupt enable control bits (DMAxIE) are located in

an IECx register in the interrupt controller, and the cor-

responding interrupt priority control bits (DMAxIP) are

located in an IPCx register in the interrupt controller.

7.2

DMAC Operating Modes

Each DMA channel has its own status and control reg-

ister (DMAxCON) that is used to configure the channel

to support the following operating modes:

• Word or byte size data transfers

• Peripheral to DMA RAM or DMA RAM to

peripheral transfers

• Post-increment or static DMA RAM address

• One-shot or continuous block transfers

• Auto-switch between two start addresses after

each transfer complete (Ping-Pong mode)

• Force a single DMA transfer (Manual mode)

Each DMA channel can be independently configured

to:

• Select from one of 19 DMA request sources

• Manually enable or disable the DMA channel

• Interrupt the CPU when the transfer is half or fully

complete

DMA channel interrupts are routed to the interrupt con-

troller module and enabled through associated enable

flags.

The channel DMA RAM and peripheral write collision

Faults are combined into a single DMAC error trap

(Level 10) and are not maskable. Each channel has

DMA RAM write collision (XWCOLx) and peripheral

CPU

SRAM

DMA RAM

CPU Peripheral DS Bus

Peripheral 3

DMA

Peripheral

Non-DMA

SRAM X-Bus

PORT 2

PORT 1

Peripheral 1

DMA

Ready

Peripheral 2

DMA

Ready

DMA DS Bus

CPU

DMA

CPU

DMA

CPU

DMA

Peripheral Indirect Address

Note: CPU and DMA address buses are not shown for clarity.

DMA Controller

DMA

Channels

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