PIC24H datasheet(115/290 Pages) MICROCHIP

115 / 290 page

Preliminary

DS70175D-page 115

PIC24H

write collision (PWCOLx) status bits in the DMAC Sta-

tus register (DMACS) to allow the DMAC error trap

handler to determine the source of the Fault condition.

7.2.1

BYTE OR WORD TRANSFER

Each DMA channel can be configured to transfer

words or bytes. As usual, words can only be moved to

and from aligned (even) addresses. Bytes can be

moved to or from any (legal) address.

If the SIZE bit (DMAxCON<14>) is clear, word sized

data is transferred. The LSb of the DMA RAM Address

Post-Increment Addressing mode is enabled, the DMA

RAM Address register is incremented by 2 after every

word transfer.

If the SIZE bit is set, byte sized data is transferred. If

Post-Increment Addressing is enabled, the DMA RAM

Address register is incremented by 1 after every byte

transfer.

7.2.2

ADDRESSING MODES

The DMAC supports Register Indirect and Register

Indirect Post-Increment Addressing modes for DMA

RAM addresses (source or destination). Each channel

can select the DMA RAM Addressing mode indepen-

dently. The Peripheral SFR is always accessed using

If the AMODE<1:0> bits (DMAxCON<5:4>) are set to

‘01’,

Indirect

Addressing

without

Post-Increment is used, which implies that the DMA

RAM address remains constant.

If the AMODE<1:0> bits are clear, DMA RAM is

accessed using Register Indirect Addressing with

Post-Increment, which means the DMA RAM address

will be incremented after every access.

Any DMA channel can be configured to operate in

Peripheral Indirect Addressing mode by setting the

AMODE<1:0> bits to ‘10’. In this mode, the DMA RAM

source or destination address is partially derived from

the peripheral as well as the DMA Address registers.

Each peripheral module has a pre-assigned peripheral

indirect address which is logically ORed with the DMA

Start Address register to obtain the effective DMA RAM

address. The DMA RAM Start Address register value

must be aligned to a power-of-two boundary.

7.2.3

DMA TRANSFER DIRECTION

Each DMA channel can be configured to transfer data

from a peripheral to DMA RAM, or from DMA RAM to a

peripheral.

If the DIR bit (DMAxCON<13>) is clear, the reads

occur from a peripheral SFR (using the DMA Periph-

eral Address register, DMAxPAD) and the writes are

directed to the DMA RAM (using the DMA RAM

Address register).

If the DIR bit (DMAxCON<13>) is set, the reads occur

from the DMA RAM (using the DMA RAM Address

(using

the

DMA

Peripheral

Address

DMAxPAD).

7.2.4

NULL DATA PERIPHERAL WRITE

MODE

If the NULLW bit (DMAxCON<11>) is set, a null data

write to the peripheral SFR is performed in addition to

a data transfer from the peripheral SFR to DMA RAM

(assuming the DIR bit is clear). This mode is most use-

ful in applications in which sequential reception of data

is required without any data transmission.

Note:

DMAxCNT value is independent of data

transfer size (byte/word). If an address off-

set is required, a 1-bit left shift of the

counter is required to generate the correct

offset for (aligned) word transfers.

Note:

Only the ECAN and A/D modules can

utilize Peripheral Indirect Addressing.

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