PFS154 datasheet(68/91 Pages) PADAUK

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PFS154

8bit MTP Type IO Controller

Page 68 of 91

PDK-DS-PFS154_CN_V105 –Jun. 9, 2020

6.33. PWMG0 Duty Value Low Register (pwmg0dtl), IO address = 0x23

Bit

Reset

R/W

Description

7 - 5

000

Duty values bit [2:0] of PWMG0.

4 - 0

Reserved

Note: It’s necessary to write PWMG0 Duty_Value Low Register before writing PWMG0 Duty_Value High Register.

6.34. PWMG1 control Register (pwmg1c), IO address = 0x26

Bit

Reset

R/W

Description

R/W

Enable PWMG1. 0 / 1 : disable / enable.

Output of PWMG1.

R/W

Enable to inverse the polarity of PWMG1 output. 0 / 1 : disable / enable.

R/W

PWMG1 counter reset.

Writing “1” to clear PWMG1 counter and this bit will be self clear to 0 after counter

reset.

3 - 1

R/W

Select PWMG1 output pin.

000: none

001: PB6

011: PA4

100: PB7

Others: reserved

R/W

Clock source of PWMG1. 0: SYSCLK, 1: IHRC

6.35. PWMG1 Scalar Register (pwmg1s), IO address = 0x27

Bit

Reset

R/W

Description

PWMG1 interrupt mode.

0: Generate interrupt when counter matches the duty value

1: Generate interrupt when counter is 0.

6 - 5

PWMG1 clock pre-scalar.

00 : ÷1

01 : ÷4

10 : ÷16

11 : ÷64

4 - 0

PWMG1 clock divider.

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