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DRV8353FSRTAR Scheda tecnica(PDF) 68 Page - Texas Instruments |
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DRV8353FSRTAR Scheda tecnica(HTML) 68 Page - Texas Instruments |
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68 / 97 page ![]() 8.6.2.3 Gate Drive LS Register (address = 0x04h) The gate drive LS register is shown in Figure 8-46 and described in Table 8-16. Register access type: Read/Write Figure 8-46. Gate Drive LS Register 10 9 8 7 6 5 4 3 2 1 0 CBC TDRIVE IDRIVEP_LS IDRIVEN_LS R/W-1b R/W-11b R/W-1111b R/W-1111b Table 8-16. Gate Drive LS Register Field Descriptions Bit Field Type Default Description 10 CBC R/W 1b Active only when OCP_MODE = 01b 0b = For VDS_OCP and SEN_OCP, the fault is cleared after tRETRY 1b = For VDS_OCP and SEN_OCP, the fault is cleared when a new PWM input is given or after tRETRY 9-8 TDRIVE R/W 11b 00b = 500-ns peak gate-current drive time 01b = 1000-ns peak gate-current drive time 10b = 2000-ns peak gate-current drive time 11b = 4000-ns peak gate-current drive time 7-4 IDRIVEP_LS R/W 1111b 0000b = 50 mA 0001b = 50 mA 0010b = 100 mA 0011b = 150 mA 0100b = 300 mA 0101b = 350 mA 0110b = 400 mA 0111b = 450 mA 1000b = 550 mA 1001b = 600 mA 1010b = 650 mA 1011b = 700 mA 1100b = 850 mA 1101b = 900 mA 1110b = 950 mA 1111b = 1000 mA DRV8350F, DRV8353F, DRV8350RF, DRV8353RF SLVSFV1 – SEPTEMBER 2020 www.ti.com 68 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: DRV8350F DRV8353F DRV8350RF DRV8353RF |
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