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DRV8353FSRTAR Scheda tecnica(PDF) 8 Page - Texas Instruments

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Il numero della parte DRV8353FSRTAR
Spiegazioni elettronici  DRV835xF 100-V Three-Phase Smart Gate Driver
PDF  97 Pages
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

DRV8353FSRTAR Scheda tecnica(HTML) 8 Page - Texas Instruments

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background image
1
GND
36
INHB
2
VGLS
35
INLA
3
CPL
34
INHA
4
CPH
33
ENABLE
5
VM
32
GAIN
6
VDRAIN
31
VDS
7
VCP
30
IDRIVE
8
GHA
29
MODE
9
SHA
28
nFAULT
10
GLA
27
AGND
11
SPA
26
VREF
12
SNA
25
SOA
Not to scale
Thermal
Pad
Figure 6-7. DRV8353RFH RGZ Package 48-Pin
VQFN With Exposed Thermal Pad Top View
1
GND
36
INHB
2
VGLS
35
INLA
3
CPL
34
INHA
4
CPH
33
ENABLE
5
VM
32
nSCS
6
VDRAIN
31
SCLK
7
VCP
30
SDI
8
GHA
29
SDO
9
SHA
28
nFAULT
10
GLA
27
AGND
11
SPA
26
VREF
12
SNA
25
SOA
Not to scale
Thermal
Pad
Figure 6-8. DRV8353RFS RGZ Package 48-Pin
VQFN With Exposed Thermal Pad Top View
Pin Functions—48-Pin DRV8353FR Devices
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
DRV8353RFH
DRV8353RFS
AGND
27
27
PWR
Device analog ground. Connect to system ground.
BST
45
45
PWR
Buck regulator bootstrap input. Connect a X5R or X7R, 0.01-µF, 16-V, capacitor between the BST and SW pins.
CPH
4
4
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
CPL
3
3
PWR
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
pins.
DGND
41
41
PWR
Device ground. Connect to system ground.
DVDD
40
40
PWR
5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and DGND pins. This
regulator can source up to 10 mA externally.
ENABLE
33
33
I
Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be
used to reset fault conditions.
FB
48
48
I
Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage.
GAIN
32
—
I
Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
GND
1
1
PWR
Device power ground. Connect to system ground.
GHA
8
8
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB
17
17
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC
18
18
O
High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA
10
10
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB
15
15
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC
20
20
O
Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
IDRIVE
30
—
I
Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA
34
34
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB
36
36
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC
38
38
I
High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA
35
35
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB
37
37
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC
39
39
I
Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE
29
—
I
PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
nFAULT
28
28
OD
Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS
—
32
I
Serial chip select. A logic low on this pin enables serial interface communication.
RCL
46
46
I
Current limit off time set input. Connect a resistor between RCL and GND.
DRV8350F, DRV8353F, DRV8350RF, DRV8353RF
SLVSFV1 – SEPTEMBER 2020
www.ti.com
8
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Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: DRV8350F DRV8353F DRV8350RF DRV8353RF



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