iCE40 LP/HX Family

Data Sheet

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30

FPGA-DS-02029-3.5

4.22. Timing Adders

Over recommended operating conditions.

Table 4.23. Timing Adders – LP Devices*

Input Adjusters

LVDS25

–0.18

ns

subLVDS

0.82

ns

LVCMOS33

0.18

ns

LVCMOS25

0.00

ns

LVCMOS18

0.19

ns

Output Adjusters

LVDS25E

0.00

ns

subLVDSE

1.32

ns

LVCMOS33

–0.12

ns

LVCMOS25

0.00

ns

LVCMOS18

1.32

ns

*Notes:



Timing adders are relative to LVCMOS25 and characterized but not tested on every device.



LVCMOS timing measured with the load specified in the Switching Test Condition table.



All other standards tested according to the appropriate specifications.



Commercial timing numbers are shown.



Not all I/O standards are supported for all banks. See the Architecture section of this data sheet for details.

Over recommended operating conditions.

Table 4.24. Timing Adders – HX Devices*

Input Adjusters

LVDS25

0.13

ns

subLVDS

1.03

ns

LVCMOS33

0.16

ns

LVCMOS25

0.00

ns

LVCMOS18

0.23

ns

Output Adjusters

LVDS25E

0.00

ns

subLVDSE

1.76

ns

LVCMOS33

0.17

ns

LVCMOS25

0.00

ns

LVCMOS18

1.76

ns

*Notes:



Timing adders are relative to LVCMOS25 and characterized but not tested on every device.



LVCMOS timing measured with the load specified in the Switching Test Condition table.



All other standards tested according to the appropriate specifications.



Commercial timing numbers are shown.



Not all I/O standards are supported for all banks. See the Architecture section of this data sheet for details.