iCE40 LP/HX Family

Data Sheet

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FPGA-DS-02029-3.5

5. Pinout Information

5.1. Signal Descriptions

5.1.1. General Purpose

Signal Name

I/O

Description

IO[Bank]_[Row/Column

Number][A/B]

I/O

[Bank] indicates the bank of the device on which the pad is located.

[Number] indicates IO number on the device.

IO[Bank]_[Row/Column

Number][A/B]

I/O

[Bank] indicates the bank of the device on which the pad is located.

[Number] indicates IO number on the device.

[A/B] indicates the differential I/O. 'A' = negative input. 'B' = positive input.

HCIO[Bank]_[Number]

I/O

High Current IO. [Bank] indicates the bank of the device on which the pad is

located. [Number] indicates IO number.

NC

—

No connect

GND

—

GND – Ground. Dedicated pins. It is recommended that all GNDs are tied

together.

VCC

—

VCC – The power supply pins for core logic. Dedicated pins. It is

recommended that all VCCs are tied to the same supply.

VCCIO_x

—

VCCIO – The power supply pins for I/O Bank x. Dedicated pins. All VCCIOs

located in the same bank are tied to the same supply.

5.1.2. PLL and Global Functions (Used as user-programmable I/O pins when not used for PLL or

clock pins)

Signal Name

I/O

Description

VCCPLLx

—

PLL VCC – Power. Dedicated pins. The PLL requires a separate power and

ground that is quiet and stable to reduce the output clock jitter of the PLL.

GNDPLLx

—

PLL GND – Ground. Dedicated pins. The sysCLOCK PLL has the DC ground

connection made on the FPGA, so the external PLL ground connection

(GNDPLL) must NOT be connected to the board’s ground.

GBINx

—

Global pads. Two per side.

5.1.3. Programming and Configuration

Signal Name

I/O

Description

CBSEL[0:1]

I/O

Dual function pins. I/Os when not used as CBSEL. Optional ColdBoot

configuration Select input, if ColdBoot mode is enabled.

CRESET_B

I

Configuration Reset, active Low. Dedicated input. No internal pull-up

resistor. Either actively drive externally or connect a 10 kΩ pull-up resistor

to VCCIO_2.

CDONE

I/O

Configuration Done. Includes a permanent weak pull-up resistor to

VCCIO_2. If driving external devices with CDONE output, an external pull-

up resistor to VCCIO_2 may be required. Refer to the iCE40 Programming

and Configuration (FPGA-TN-02001) for more details. Following device

configuration the iCE40LP640 and iCE40LP1K in the SWG16 package CDONE

pin can be used as a user output.