iCE40 LP/HX Family

Data Sheet

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8

FPGA-DS-02029-3.5

3. Architecture

3.1. Architecture Overview

The iCE40 LP/HX family architecture contains an array of Programmable Logic Blocks (PLB), sysCLOCK™ PLLs,

Nonvolatile Programmable Configuration Memory (NVCM) and blocks of sysMEM Embedded Block RAM (EBR)

surrounded by Programmable I/O (PIO). Figure 3.1 shows the block diagram of the iCE40LP/HX1K device.

Programmable

Lo gic Block (PLB)

I/O Bank 0

Programmable Interconnect

I/O Bank 2

NVCM

Flip-flop with Enable

and Reset Controls

Non-volatile

Configuration Memory

(NVCM)

Phase-Locked

Loop

Carry Logic

4-Input Look-up

Table (LUT4)

PLL

SPI

Bank

Figure 3.1. iCE40LP/HX1K Device, Top View

The logic blocks, Programmable Logic Blocks (PLB) and sysMEM EBR blocks, are arranged in a two-dimensional grid with

rows and columns. Each column has either logic blocks or EBR blocks. The PIO cells are located at the periphery of the

device, arranged in banks. The PLB contains the building blocks for logic, arithmetic, and register functions. The PIOs

utilize a flexible I/O buffer referred to as a sysI/O buffer that supports operation with a variety of interface standards.

The blocks are connected with many vertical and horizontal routing channel resources. The place and route software

tool automatically allocates these routing resources.

In the iCE40 LP/HX family, there are up to four independent sysI/O banks. Note on some packages VCCIO banks are tied

together. There are different types of I/O buffers on the different banks. Refer to the details in later sections of this