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ADL5206ACPZ-R7 Scheda tecnica(PDF) 5 Page - Analog Devices |
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ADL5206ACPZ-R7 Scheda tecnica(HTML) 5 Page - Analog Devices |
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5 / 25 page ![]() Data Sheet ADL5206 Rev. 0 | Page 5 of 25 3.3 V Supply1 5 V Supply1 Parameter2 Test Conditions/Comments Min Typ Max Min Typ Max Unit DIGITAL INTERFACE Input Voltage MODE1, MODE0, PWUP, LATCH, and SDIO pins Logic High (VIH) 2 VPOS 2 3.3 V Logic Low (VIL) 0 1.0 0 1.0 V Input Leakage Current Digital VIN = 0 V to 3.3 V ±3 ±3 µA Output Voltage SDIO pin Logic High (VOH) Output high current (IOH) = −2 mA 2.4 2.4 2.4 Logic Low (VOL) Output low current (IOL) = 2 mA 0.5 0.5 POWER INTERFACE Supply Voltage (VPOS) VPOS pin 3.15 3.3 3.45 4.75 5 5.25 V Quiescent Current 87 112 mA Power-Down Current PWUP pin = low 8 8 mA 1 The 3.3 V supply is low power mode, and the 5 V supply is high performance mode. 2 When referring to a single function of a multifunction pin in the specifications table, only the portion of the pin name that is relevant to the specification is listed. For full pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section. 3 The maximum input swing of 6.2 V p-p is for the lowest gain setting of 2 dB. As the gain setting increases, the maximum input swing must be reduced correspondingly to maintain the same maximum output swing. The maximum output swing is based on P1dB. |
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