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TMS320F28375DPZP Scheda tecnica(PDF) 153 Page - Texas Instruments

Il numero della parte TMS320F28375DPZP
Spiegazioni elettronici  TMS320F2837xD Dual-Core Microcontrollers
PDF  226 Pages
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Produttore elettronici  TI [Texas Instruments]
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TMS320F28375DPZP Scheda tecnica(HTML) 153 Page - Texas Instruments

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8.12.3.1 McBSP Electrical Data and Timing
8.12.3.1.1 McBSP Transmit and Receive Timing
Section 8.12.3.1.1.1 shows the McBSP timing requirements. Section 8.12.3.1.1.2 shows the McBSP switching
characteristics. Figure 8-64 and Figure 8-65 show the McBSP timing diagrams.
8.12.3.1.1.1 McBSP Timing Requirements
NO.(1)
(2)
MIN
MAX
UNIT
McBSP module clock (CLKG, CLKX, CLKR) range
1
kHz
25
MHz
McBSP module cycle time (CLKG, CLKX, CLKR) range
40
ns
1
ms
M11
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2P
ns
M12
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
P – 7
ns
M13
tr(CKRX)
Rise time, CLKR/X
CLKR/X ext
7
ns
M14
tf(CKRX)
Fall time, CLKR/X
CLKR/X ext
7
ns
M15
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR int
18
ns
CLKR ext
2
M16
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int
0
ns
CLKR ext
6
M17
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR int
18
ns
CLKR ext
5
M18
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int
0
ns
CLKR ext
3
M19
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX int
18
ns
CLKX ext
2
M20
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int
0
ns
CLKX ext
6
(1)
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2)
2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG / (1 + CLKGDV). CLKSRG can be LSPCLK,
CLKX, CLKR as source. CLKSRG ≤ (SYSCLK/2).
www.ti.com
TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D
TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D
SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021
Copyright © 2021 Texas Instruments Incorporated
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