TMS320F28375DPZP datasheet(156/226 Pages) TI

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8.12.3.1.2 McBSP as SPI Master or Slave Timing

Section 8.12.3.1.2.1 lists the McBSP as SPI master timing requirements. Section 8.12.3.1.2.2 lists the McBSP as

SPI master switching characteristics. Section 8.12.3.1.2.3 lists the McBSP as SPI slave timing requirements.

Section 8.12.3.1.2.4 lists the McBSP as SPI slave switching characteristics.

Figure 8-66 through Figure 8-69 show the McBSP as SPI master or slave timing diagrams.

8.12.3.1.2.1 McBSP as SPI Master Timing Requirements

NO.

MIN

MAX

UNIT

CLOCK

tc(CLKG)

Cycle time, CLKG(1)

2 * tc(LSPCLK)

Cycle time, LSPCLK(1)

tc(LSPCLK)

M33,

M42,

M52,

M61

tc(CKX)

Cycle time, CLKX

CLKSTP = 10b, CLKXP = 0

M30

tsu(DRV-CKXL)

Setup time, DR valid before CLKX low

M31

th(CKXL-DRV)

Hold time, DR valid after CLKX low

CLKSTP = 11b, CLKXP = 0

M39

tsu(DRV-CKXH)

Setup time, DR valid before CLKX high

M40

th(CKXH-DRV)

Hold time, DR valid after CLKX high

CLKSTP = 10b, CLKXP = 1

M49

tsu(DRV-CKXH)

Setup time, DR valid before CLKX high

M50

th(CKXH-DRV)

Hold time, DR valid after CLKX high

CLKSTP = 11b, CLKXP = 1

M58

tsu(DRV-CKXL)

Setup time, DR valid before CLKX low

M59

th(CKXL-DRV)

Hold time, DR valid after CLKX low

(1)

CLKG should be configured to LSPCLK/2 by setting CLKSM = 1 and CLKGDV = 1

TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D

TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021

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