VR4102 datasheet(177/701 Pages) NEC

177 / 701 page

CHAPTER 6 EXCEPTION PROCESSING

177

6.4.4 Cold Reset Exception

Cause

The Cold Reset exception occurs when the ColdReset# signal (internal) is asserted and then deasserted. This

exception is not maskable. The Reset# signal (internal) must be asserted along with the ColdReset# signal (for

details, see Chapter 7).

Processing

The CPU provides a special interrupt vector for this exception:

0xBFC0 0000 (virtual) in 32-bit mode

0xFFFF FFFF BFC0 0000 (virtual) in 64-bit mode

The Cold Reset vector resides in unmapped and uncached CPU address space, so the hardware need not

initialize the TLB or the cache to process this exception. It also means the processor can fetch and execute

instructions while the caches and virtual memory are in an undefined state.

The contents of all registers in the CPU are undefined when this exception occurs, except for the following

When ERL bit of the Status register is 0, the program counter’s value at the exception occurrence is saved

to the EPC register.

TS and SR of the Status register are cleared to 0.

ERL and BEV of the Status register are set to 1.

The Random register is initialized to the value of its upper bound (31) (refer to 5.4.2 Random Register (1)).

The Wired register is initialized to 0.

Bits 31 to 28 of the Config register are set to 0, and bits 22 to 3 to 0x04800.

All other bits are undefined.

Servicing

The Cold Reset exception is serviced by:

Initializing all processor registers, coprocessor registers, TLB, caches, and the memory system

Performing diagnostic tests

Bootstrapping the operating system

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