VR4102 datasheet(99/701 Pages) NEC

99 / 701 page

CHAPTER 4 VR4102 PIPELINE

This chapter describes the basic operation of the VR4102 processor pipeline, which includes descriptions of the

delay slots (instructions that follow a branch or load instruction in the pipeline), interrupts to the pipeline flow caused

by interlocks and exceptions, and CP0 hazards.

4.1 PIPELINE STAGES

The VR4102 has a five-stage instruction pipeline; each stage takes one PCycle (one cycle of Pclock), and each

PCycle has two phases:

)1 and )2, as shown in Figure 4-1. Thus, the execution of each instruction takes at least

5 PCycles. An instruction can take longer - for example, if the required data is not in the cache, the data must be

retrieved from main memory. Once the pipeline has been filled, five instructions are executed simultaneously.

Figure 4-1. Pipeline Stages

Cycle

Phase

PCycle

PClock

The five pipeline stages are:

— IF - Instruction cache fetch

— RF - Register fetch

— EX - Execution

— DC - Data cache fetch

— WB - Write back

Figure 4-2 shows the five stages of the instruction pipeline. In this figure, a row indicates the execution process

of each instruction, and a column indicates the processes executed simultaneously.

VR4102 Scheda tecnica(PDF) 99 Page - NEC