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VR4102 Scheda tecnica(PDF) 44 Page - NEC

Il numero della parte VR4102
Spiegazioni elettronici  64/32-bit Microprocessor
PDF  701 Pages
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Produttore elettronici  NEC [NEC]
Homepage  http://www.nec.com/
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VR4102 Scheda tecnica(HTML) 44 Page - NEC

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CHAPTER 1 INTRODUCTION
44
(5) Coprocessor 0 (CP0)
CP0 incorporates a memory management unit (MMU) and exception handling function. MMU checks whether
there is an access between different memory segments (user, supervisor, and kernel) by executing address
conversion. The translation lookaside buffer (TLB) converts virtual addresses to physical addresses.
(6) Data cache
The data cache employs direct mapping, virtual index, physical tag, and write back. Its capacity is 1K bytes.



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