VR4102 datasheet(166/701 Pages) NEC

166 / 701 page

CHAPTER 6 EXCEPTION PROCESSING

166

Table 6-2. Cause Register Exception Code Field

Exception code

Mnemonic

Description

Int

Interrupt exception

Mod

TLB Modified exception

TLBL

TLB Refill exception (load or fetch)

TLBS

TLB Refill exception (store)

AdEL

Address Error exception (load or fetch)

AdES

Address Error exception (store)

IBE

Bus Error exception (instruction fetch)

DBE

Bus Error exception (data load or store)

Sys

System Call exception

Breakpoint exception

Reserved Instruction exception

CpU

Coprocessor Unusable exception

Integer Overflow exception

Trap exception

14 to 22

•

Reserved for future use

WATCH

Watch exception

24 to 31

•

Reserved for future use

The VR4102 has eight interrupt request sources, IP7 to IP0.

For the detailed description of interrupts, refer to Chapter 9.

(1) IP7

This bit indicates whether there is a timer interrupt request.

It is set when the values of Count register and Compare register match.

(2) IP6 to IP2

IP6 to IP2 reflect the state of the interrupt request signal of the CPU core.

(3) IP1 and IP0

These bits are used to set/clear a software interrupt request.

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