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PIMXRT406LCJM4A Scheda tecnica(PDF) 9 Page - NXP Semiconductors |
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PIMXRT406LCJM4A Scheda tecnica(HTML) 9 Page - NXP Semiconductors |
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9 / 71 page ![]() Modules list i.MX RT1015 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 03/2021 NXP Semiconductors 9 GPT1 GPT2 General Purpose Timer Timer Peripherals Each GPT is a 32-bit “free-running” or “set and forget” mode timer with programmable prescaler and compare and capture register. A timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in “set and forget” mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock. KPP Keypad Port Human Machine Interfaces The KPP is a 16-bit peripheral that can be used as a keypad matrix interface or as general purpose input/output (I/O). It supports 4 x 4 external key pad matrix. Main features are: • Multiple-key detection • Long key-press detection • Standby key-press detection • Supports a 2-point and 3-point contact key matrix LPI2C1 LPI2C2 Low Power Inter-integrated Circuit Connectivity and Communications The LPI2C is a low power Inter-Integrated Circuit (I2C) module that supports an efficient interface to an I2C bus as a master. The I2C provides a method of communication between a number of external devices. More detailed information, see Section 4.8.2, LPI2C module timing parameters. LPSPI1 LPSPI2 Low Power Serial Peripheral Interface Connectivity and Communications The LPSPI is a low power Serial Peripheral Interface (SPI) module that support an efficient interface to an SPI bus as a master and/or a slave. • It can continue operating while the chip is in stop modes, if an appropriate clock is available • Designed for low CPU overhead, with DMA off loading of FIFO register access LPUART1 LPUART2 LPUART3 LPUART4 UART Interface Connectivity Peripherals Each of the UART modules support the following serial data transmit/receive protocols and configurations: • 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd or none) • Programmable baud rates up to 20 Mbps. MQS Medium Quality Sound Multimedia Peripherals MQS is used to generate 2-channel medium quality PWM-like audio via two standard digital GPIO pins. Table 2. i.MX RT1015 modules list (continued) Block mnemonic Block name Subsystem Brief description |
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