PIMXRT406LCJM4A datasheet(60/100 Pages) NXP

60 / 100 page

i.MX RT1020 Crossover Processors for Industrial Products, Rev. 2, 03/2021

NXP Semiconductors

Electrical characteristics

4.8

Communication interfaces

The following sections provide the information about communication interfaces.

4.8.1

LPSPI timing parameters

The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and

slave operations. Many of the transfer attributes are programmable. The following tables provide timing

characteristics for classic LPSPI timing modes.

All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as well as input

signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins.

RDAC6b

6-bit DAC reference inputs

—

VDD

—V

INLDAC6b

6-bit DAC integral non-linearity

-0.3

—

0.3

LSB4

DNLDAC6b

6-bit DAC differential non-linearity -0.15

—

0.15

LSB4

1 Typical hysteresis is measured with input voltage range limited to 0.7 to VDD - 0.7 V in high speed mode.

2 Signal swing is 100 mV.

3 Comparator initialization delay is defined as the time between software writes to the enable comparator module and the

comparator output setting to a stable level.

4 1 LSB = Vreference / 64

Table 53. LPSPI Master mode timing

Number

Symbol

Description

Min.

Max.

Units

Note

1fSCK

Frequency of operation

—

fperiph / 2

1 Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must be

guaranteed this limit is not exceeded.

2tSCK

SCK period

2 x tperiph

—ns

2 tperiph = 1 / fperiph

3tLead

Enable lead time

—

tperiph

—

4tLag

Enable lag time

—

tperiph

—

5tWSCK

Clock (SCK) high or low time

tSCK / 2 - 3

—

6tSU

Data setup time (inputs)

—

7tHI

Data hold time (inputs)

—

8tV

Data valid (after SCK edge)

—

9tHO

Data hold time (outputs)

—

Table 52. Comparator and 6-bit DAC electrical specifications (continued)

Symbol

Description

Min.

Typ.

Max.

Unit

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