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PIMXRT406LCJM4A Scheda tecnica(PDF) 87 Page - NXP Semiconductors |
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PIMXRT406LCJM4A Scheda tecnica(HTML) 87 Page - NXP Semiconductors |
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87 / 100 page  Package information and contact assignments i.MX RT1020 Crossover Processors for Industrial Products, Rev. 2, 03/2021 NXP Semiconductors 87 GPIO_SD_B1_06 25 NVCC_GPIO Digital GPIO ALT5 GPIO3.IO[26] Input Keeper GPIO_SD_B1_07 24 NVCC_GPIO Digital GPIO ALT5 GPIO3.IO[27] Input Keeper GPIO_SD_B1_08 23 NVCC_GPIO Digital GPIO ALT5 GPIO3.IO[28] Input Keeper GPIO_SD_B1_09 22 NVCC_GPIO Digital GPIO ALT5 GPIO3.IO[29] Input Keeper GPIO_SD_B1_10 21 NVCC_GPIO Digital GPIO ALT5 GPIO3.IO[30] Input Keeper GPIO_SD_B1_11 19 NVCC_GPIO Digital GPIO ALT5 GPIO3.IO[31] Input Keeper ONOFF 49 VDD_SNVS_IN Digital GPIO ALT0 src.RESET_B Input 100 K PU PMIC_ON_REQ 53 VDD_SNVS_IN Digital GPIO ALT0 snvs_lp.PMIC_ON_REQ Input 100 K PU PMIC_STBY_REQ 54 VDD_SNVS_IN Digital GPIO ALT0 ccm.PMIC_VSTBY_REQ Output 100 K PU (PKE disabled) POR_B 50 VDD_SNVS_IN Digital GPIO ALT0 src.POR_B Input 100 K PU RTC_XTALI 57 — — — — — — RTC_XTALO 58 — — — — — — TEST_MODE 51 VDD_SNVS_IN Digital GPIO ALT0 tcu.TEST_MODE Input 100 K PD USB_OTG1_CHD_B 66 — — — — — — USB_OTG1_DN 62 — — — — — — USB_OTG1_DP 63 — — — — — — USB_OTG1_VBUS 59 — — — — — — XTALI 67 — — — — — — XTALO 68 — — — — — — WAKEUP 52 VDD_SNVS_IN Digital GPIO ALT5 GPIO5.IO[0] Input 100 K PU 1 This pin output is in a high level until the system reset is complete. Table 83. 20 x 20 mm functional contact assignments (continued) |
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