DS31256_V01 datasheet(38/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

38 of 183

Bit 14/Status Bit for Local Bus Error (LBE). This status bit applies to the local bus when it is operated in PCI

bridge mode. It is set to 1 when the local bus

LRDY signal is not detected within nine LCLK periods. This

indicates to the host that an aborted local bus access has occurred. If enabled through the LBE bit in the interrupt

mask for SM (ISM), the setting of this bit causes a hardware interrupt at the PCI bus through the

PINTA signal pin

and also at the

LINT if the local bus is in configuration mode. The LBE bit is meaningless when the local bus is

operated in the configuration mode and should be ignored.

Bit 15/Status Bit for Local Bus Interrupt (LBINT). This status bit is set to 1 if the local bus

LINT signal has

been detected as asserted. This status bit is only valid when the local bus is operated in PCI bridge mode. The

LBINT bit is cleared when read and is not set again until the

LINT signal pin once again has been detected as

asserted. If enabled through the LBINT bit in the interrupt mask for SM (ISM), the setting of this bit causes a

hardware interrupt at the PCI bus through the

PINTA signal pin. The LBINT bit is meaningless when the local bus

is operated in the configuration mode and should be ignored.

ISM

Interrupt Mask Register for SM

0024h

Bit #

Name

n/a

PPERR

PSERR

SBERT

STCOFA

SRCOFA

Default

Bit #

Name

LBINT

LBE

n/a

Default

Note: Bits that are underlined are read-only; all other bits are read-write.

Bit 0/Status Bit for Receive Change-of-Frame Alignment (SRCOFA)

0 = interrupt masked

1 = interrupt unmasked

Bit 1/Status Bit for Transmit Change-of-Frame Alignment (STCOFA)

0 = interrupt masked

1 = interrupt unmasked

Bit 2/Status Bit for Change of State in BERT (SBERT)

0 = interrupt masked

1 = interrupt unmasked

Bit 3/Status Bit for PCI System Error (PSERR)

0 = interrupt masked

1 = interrupt unmasked

Bit 4/Status Bit for PCI System Error (PPERR)

0 = interrupt masked

1 = interrupt unmasked

Bit 14/Status Bit for Local Bus Error (LBE)

0 = interrupt masked

1 = interrupt unmasked

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