DS31256_V01 datasheet(52/183 Pages) MAXIM

52 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

52 of 183

CP[n]RDIS, where n = 0 to 15 for each port

Channelized Port [n] Register Data Indirect Select

See the Register Map in Section 4.

Bit #

Name

n/a

CHID6

CHID5

CHID4

CHID3

CHID2

CHID1

CHID0

Default

Bit #

Name

IAB

IARW

n/a

CPRS1

CPRS0

Default

Note: Bits that are underlined are read-only; all other bits are read-write.

Bits 0 to 6/DS0 Channel ID (CHID0 to CHID6). The number of DS0 channels used depends on whether the port

has been configured for an unchannelized application or for a channelized application. If set for a channelized

application, the number of DS0 channels depends on whether the port has been configured in the T1, E1,

4.096MHz, or 8.192MHz mode.

0000000 (00h) = DS0 channel number 0

1111111 (7Fh) = DS0 channel number 127

PORT MODE

DS0 CHANNELS

AVAILABLE

Unchannelized (RUEN/TUEN = 1)

Channelized T1 (RUEN/TUEN = 0 and RSS0/TSS0 = 0 and RSS1/TSS1 = 0)

0 to 23

Channelized E1 (RUEN/TUEN = 0 and RSS0/TSS0 = 1 and RSS1/TSS1 = 0)

0 to 31

Channelized 4.096MHz (RUEN/TUEN = 0 and RSS0/TSS0 = 0 and RSS1/TSS1 = 1)

0 to 63

Channelized 8.192MHz (RUEN/TUEN = 0 and RSS0/TSS0 = 1 and RSS1/TSS1 = 1)

0 to 127

Bit 8/Channelized PORT RAM Select Bit 0 (CPRS0); Bit 9/Channelized PORT RAM Select Bit 1 (CPRS1)

00 = channelized DS0 data (C[n]DAT[j])

01 = receive configuration (R[n]CFG[j])

10 = transmit configuration (T[n]CFG[j])

11 = illegal selection

Bit 14/Indirect Access Read/Write (IARW). When the host wishes to read data from the internal channelized

PORT RAM, this bit should be written to 1 by the host. This causes the device to begin obtaining data from the

DS0 channel location indicated by the CHID bits and the data from the PORT RAM indicated by the CPRS0 and

CPRS1 bits. During the read access, the IAB bit is set to 1. Once the data is ready to be read from the CP[n]RD

host should write this bit to 0. This causes the device to take the data that is currently present in the CP[n]RD

the CHID bits. When the device has completed the write, the IAB is set to 0.

Bit 15/Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read-only bit is set

to 1. During a read operation, this bit is set to 1 until data is ready to be read. It is set to 0 when the data is ready to

be read. During a write operation, this bit is set to 1 while the write is taking place. It is set to 0 once the write

operation has completed.

DS31256 Scheda tecnica(PDF) 52 Page - Maxim Integrated Products

DS31256 Scheda tecnica(HTML) 52 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL