MAX96708 datasheet(13/68 Pages) MAXIM

13 / 68 page

(VDVDD = VAVDD = 1.7 to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected to PCB ground, TA = -40°C to

+115°C, Typical values are at, VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25°C, unless otherwise noted.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

PARALLEL CLOCK OUTPUT (PCLKOUT)

Clock Frequency

fPCLKOUT

BWS = 1, DRS = 1, single output

6.25

12.5

MHz

BWS = 0, DRS = 1, single output

8.33

16.66

BWS = 1, DRS = 0, single output

12.5

43.5

BWS = 0, DRS = 0, single output

16.66

BWS = 1, DRS = 0, double output

BWS = 0, DRS = 0, double output

33.33

116

Data Valid Before Clock

tDVB

PCLKOUT and DOUT_, DCS = 1,

CL = 10pF or DCS = 0, CL = 5pF,

nonstaggered DOUT_

0.4T

0.5T

PCLKOUT and DOUT_, DCS = 1,

CL = 10pF or DCS = 0, CL = 5pF,

staggered DOUT_

0.35T

0.4T

Data Valid After Clock

tDVA

PCLKOUT and DOUT_, DCS = 1,

CL = 10pF or DCS = 0, CL = 5pF,

nonstaggered DOUT_

0.35T

0.4T

PCLKOUT and DOUT_, DCS = 1, CL =

10pF or DCS = 0, CL = 5pF,

staggered DOUT_

0.3T

0.35T

Clock Jitter

RMS period jitter, spread off, 1.74Gbps

PRBS pattern, UI = 1/fPCLKOUT, DBL = 1,

double output)

0.05

Period jitter; peak-to-peak, spread off,

1.74Gbps, PRBS pattern, UI = 1/fPCLKOUT,

DBL = 0, single output)

0.01

I2C/UART PORT TIMING

I2C/UART Bit Rate

9.6

1000

kbps

Output Rise Time

30% to 70%, CL = 10pF to 100pF,

1kΩ pullup to IOVDD

150

Output Fall Time

70% to 30%, CL = 10pF to 100pF,

1kΩ pullup to IOVDD

150

I2C TIMING (Figure 6)

SCL Clock Frequency

fSCL

Low fSCL range: (I2CMSTBT = 010,

I2CSLVSH = 10)

9.6

100

kHz

Mid fSCL range: (I2CMSTBT 101,

I2CSLVSH = 01)

>100

400

High fSCL range: (I2CMSTBT = 111,

I2CSLVSH = 00)

>400

1000

AC Electrical Characteristics

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MAX96708

14-Bit GMSL Deserializer

with Coax or STP Cable Input

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