MPC8343ECVRADDB datasheet(11/80 Pages) NXP

11 / 80 page

MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11

Freescale Semiconductor

Clock Input Timing

Table 5 shows the estimated typical I/O power dissipation for MPC8343EA.

Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the device.

4.1

DC Electrical Characteristics

Table 6 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8343EA.

Table 5. MPC8343EA Typical I/O Power Dissipation

Interface

Parameter

DDR2

GVDD

(1.8 V)

DDR1

GVDD

(2.5 V)

OVDD

(3.3 V)

LVDD

(3.3 V)

LVDD

(2.5 V)

Unit

Comments

DDR I/O

65% utilization

2.5 V

Rs = 20

Rt = 50

2 pair of clocks

200 MHz, 32 bits

0.31

0.42

—

266 MHz, 32 bits

0.35

0.5

—

PCI I/O

load = 30 pF

33 MHz, 32 bits

—

0.04

—

66 MHz, 32 bits

—

0.07

—

Local bus I/O

load = 25 pF

167 MHz, 32 bits

—

0.34

—

133 MHz, 32 bits

—

0.27

—

83 MHz, 32 bits

—

0.17

—

66 MHz, 32 bits

—

0.14

—

50 MHz, 32 bits

—

0.11

—

TSEC I/O

load = 25 pF

MII

—

0.01

—

Multiply by number

of interfaces used.

GMII or TBI

—

0.06

—

RGMII or RTBI

—

0.04

USB

12 MHz

—

0.01

—

480 MHz

—

0.2

—

Other I/O

—

0.01

—

Table 6. CLKIN DC Timing Specifications

Parameter

Condition

Symbol

Min

Max

Unit

Input high voltage

—

VIH

2.7

OVDD +0.3

Input low voltage

—

VIL

–0.3

0.4

CLKIN input current

0 V

≤ V

IN ≤ OVDD

IIN

—

±10

μA

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