ST25DV64KC datasheet(70/203 Pages) STMICROELECTRONICS

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Table 92. Operating modes

Mode

RW bit

Bytes

Initial sequence

Current address read

Start, device select, RW = 1

Random address read

Start, device select, RW = 0, address

reStart, device select, RW = 1

Sequential read

≥ 1

Similar to current or random address read

Byte write

Start, device select, RW = 0

Sequential write

≤ 256 byte

Start, device select, RW = 0

6.4

I²C Write operations

Following a Start condition, the bus master sends a device select code with the Read/Write bit (RW) reset to 0.

The device acknowledges this, and waits for two address bytes. The device responds to each address byte with

an acknowledge bit, and then waits for the data byte.

Each data byte in the memory has a 16-bit (two-byte wide) address. The most significant byte (see

Table 93. Address most significant byte) is sent first, followed by the least significant byte (see Table 94. Address

least significant byte). Bits b15 to b0 form the address of the byte in memory.

Table 93. Address most significant byte

b15

b14

b13

b12

b11

b10

Table 94. Address least significant byte

When the bus master generates a Stop condition immediately after the Ack bit (in the tenth-bit time slot), either at

the end of a byte write or a sequential write, the internal write cycle is triggered. A Stop condition at any other time

slot does not trigger the internal write cycle.

After the Stop condition, the delay tW, and the successful completion of a Write operation, the device’s internal

address counter is incremented automatically, to point to the next byte address after the last one that was

modified.

After an unsuccessful write operation, ST25DVxxKC enters in I²C dead state: internal address counter is not

incremented, and is waiting for a full new I²C instruction (address counter stops to be incremented after the first

NoAck bit).

During the internal write cycle, the serial data (SDA) signal is disabled internally, and the device does not respond

to any requests.

Caution:

I²C Writing data in user memory (EEPROM), transit via the 256 bytes fast transfer mode's buffer. Consequently

fast transfer mode must be deactivated before starting any write operation in user memory, otherwise the

command is NotACK, the programming is not done and device goes in standby mode.

6.4.1

I2C Byte write

After the device select code and the address bytes, the bus master sends one data byte.

If byte write is not inhibited, the device replies with Ack.

If byte write is inhibited, the device replies with NoAck.

The bus master terminates the transfer by generating a Stop condition (see Figure 32. Write mode sequences

when write is not inhibited).

For byte write in EEPROM (user memory or system configuration), internal programming starts after the STOP

condition, for a duration of tW (as defined in Table 249. I2C DC characteristics up to 85 °C and Table 250. I2C DC

characteristics up to 125 °C).

ST25DV04KC ST25DV16KC ST25DV64KC

I²C Write operations

DS13519 - Rev 3

page 70/203

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