ST25DV64KC datasheet(72/203 Pages) STMICROELECTRONICS

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Figure 32. Write mode sequences when write is not inhibited

Byte

Write

Dev Select

Byte address Byte address

Data in

Sequential

Write

Dev Select

Byte address Byte address

Data in 1

Data in 2

Data in N

ACK

R/W

ACK

R/W

ACK

Note:

N ≤ 256

Figure 33. Write mode sequences when write is inhibited

Byte

Write

Dev select

Byte address

Data in

Sequential

Write

Dev select

Byte address

Data in 1

Data in 2

Sequential

Write(cont'd)

Data in N

ACK

NO ACK

R/W

ACK

NO ACK

R/W

NO ACK

Note:

N ≤ 256

6.4.3

Minimizing system delays by polling on ACK

During the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from

its internal latches to the memory cells. The maximum I²C write time (tw) is shown in Table 251. I2C AC

characteristics up to 85 °C and Table 252. I2C AC characteristics up to 125 °C, but the typical time is shorter. To

make use of this, a polling sequence can be used by the bus master.

The sequence, as shown in Figure 34. Write cycle polling flowchart using ACK is:

•

Initial condition: a write cycle is in progress.

•

Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new

instruction).

•

Step 2: if the device is busy with the internal write cycle, no Ack is returned and the bus master goes back

to Step 1. If the device has terminated the internal write cycle, it responds with an Ack, indicating that the

device is ready to receive the second part of the instruction (the first byte of this instruction having been sent

during Step 1).

ST25DV04KC ST25DV16KC ST25DV64KC

I²C Write operations

DS13519 - Rev 3

page 72/203

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