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OPA387DBVT Scheda tecnica(PDF) 19 Page - Texas Instruments

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Il numero della parte OPA387DBVT
Spiegazioni elettronici  OPAx387 Ultra-High Precision, Zero-Drift, Low-Input-Bias-Current Op Amps
PDF  37 Pages
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
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OPA387DBVT Scheda tecnica(HTML) 19 Page - Texas Instruments

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9 Power Supply Recommendations
The OPAx387 family of devices is specified for operation from 1.7 V to 5.5 V for single supplies, and ±0.85 V to
±2.75 V for dual supplies. Key parameters that can exhibit significant variance with regard to operating voltage
are presented in Section 6.7.
CAUTION
Supply voltages greater than 6 V can permanently damage the device (see Section 6.1).
10 Layout
10.1 Layout Guidelines
Pay attention to good layout practice. Keep traces short and, when possible, use a printed-circuit board (PCB)
ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1-µF
capacitor close to the supply pins. These guidelines must be applied throughout the analog circuit to improve
performance, and provide benefits such as reducing the electromagnetic interference (EMI) susceptibility.
For lowest offset voltage and precision performance, optimize circuit layout and mechanical conditions. Avoid
temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed from
connecting dissimilar conductors. Cancel these thermally-generated potentials by making sure that the potentials
are equal on both input pins. Other layout and design considerations include:
• Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
• Thermally isolate components from power supplies or other heat sources.
• Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Follow these guidelines to reduce the likelihood of junctions being at different temperatures, which can cause
thermoelectric voltage drift of 0.1 µV/°C or higher depending on materials used.
10.2 Layout Example
+
V
IN
V
OUT
R
G
R
F
R
IN
GND
Figure 10-1. Schematic Representation
CBYPASS
Minimize
parasitic
inductance by
placing bypass
capacitor close
to V+.
RF
Route trace under package for output to
feedback resistor connection.
V+
–IN
+IN
V–
OUT
Keep high
impedance
input signal
away from
noisy traces.
VIN
VOUT
VS
RG
Figure 10-2. Layout Example
www.ti.com
OPA387, OPA2387, OPA4387
SBOS984F – NOVEMBER 2020 – REVISED FEBRUARY 2022
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
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Product Folder Links: OPA387 OPA2387 OPA4387



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