RT600 datasheet(2/167 Pages) NXP

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RT600

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Product data sheet

Rev. 2.0 — 1 April 2022

2 of 165

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

interface supporting up to eight channels and Voice Activation Detect, one I3C interface,

one high-speed SPI interface and seven configurable serial interfaces that can be

configured as a USART, SPI, I2C or I2S bus interface, each including a FIFO. When

configured as USARTs the serial interfaces have the option to operate in deep-sleep

mode using the 32 kHz oscillator or an external clock. There is a dedicated fractional baud

rate generator for each of the serial interfaces.

Timing peripherals include one advanced, 32-bit SCTimer/PWM module, five general

purpose 32-bit timer/counters with PWM capability, a 24-bit, multiple-channel multi-rate

timer, two windowed watchdog timers, a system tick timer with capture capability, and a

Real-time clock module with independent power and a dedicated oscillator. A common OS

Event Timer is provided for synchronized event generation and timestamping between the

two CPUs.

There are two general purpose DMA engines which can service most of the peripherals

described in this section. The two DMA engines may be assigned to different CPUs and/or

one may be used for secure operations, the other for non-secure.

Mailboxes and hardware semaphores are provided to facilitate inter-core communication.

A variety of oscillators and PLLs are available as clock sources throughout the system.

1.2 Shared system SRAM

The entire system SRAM space of up to 4.5 MB is divided into up to 30 separate

partitions, which are accessible to both CPUs, both DMA engines, and all other AHB bus

masters. The HiFi4 CPU accesses the RAM via a dedicated 256-bit interface. Cache (with

single-cycle access) is provided on this interface to improve performance. All other

masters, including the Cortex-M33 processor and the DMA engines, access RAM via the

main 32-bit AHB bus. These accesses are all single-cycle. Hardware interface modules

arbitrate access to each RAM partition between the HiFi4 and the AHB bus.

Under software control, each of the 30 individual SRAM partitions can be used exclusively

as code or as data, dedicated either CPU, or shared among the various masters. Each

partition can be independently placed in a low-power retention mode or powered off

entirely.

In addition to the shared SRAM, a total of 128 KB (64 KB code, 64 KB data) of local,

Tightly-Coupled Memory (TCM) is provided for the exclusive use of the HiFi4 DSP

processor. Access to this memory is single-cycle.

2. Features and benefits



Control processor core



Arm Cortex-M33 processor, running at frequencies of up to 300 MHz.



Arm TrustZone.



Arm Cortex-M33 built-in Memory Protection Unit (MPU) supporting eight regions



Hardware Floating Point Unit (FPU).



Arm Cortex-M33 built-in Nested Vectored Interrupt Controller (NVIC).



Non-maskable Interrupt (NMI) input.

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