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RT600 Scheda tecnica(PDF) 84 Page - NXP Semiconductors |
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RT600 Scheda tecnica(HTML) 84 Page - NXP Semiconductors |
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84 / 167 page ![]() RT600 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors B.V. 2022. All rights reserved. Product data sheet Rev. 2.0 — 1 April 2022 84 of 165 NXP Semiconductors RT600 Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4 Audio DSP CPUs 10.18.7 Micro-Tick Timer A 32-bit MicroTick timer that runs from the 1 MHz low-power oscillator. This timer can wake up the device from reduced power modes up to deep-sleep, with extremely low power consumption. The MicroTick timer has an added timestamp feature in the form of 4 capture registers. 10.18.7.1 Features • Ultra simple, ultra-low power timer that can run and wake up the device in reduced power modes other than deep power-down. • Write once to start. • Interrupt or software polling. • Four capture registers that can be triggered by external pin transitions. 10.19 Other digital peripherals 10.19.1 DMA controller The DMA controller allows peripheral-to memory, memory-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional DMA transfers for a single source and destination. Two identical DMA controllers are provided on the RT600. The user may elect to dedicate one of these to the Cortex M-33 CPU and the other for use by the DSP CPU and/or one may be used as a secure DMA the other non-secure. 10.19.1.1 Features • One channel per on-chip peripheral direction: typically one for input and one for output for most peripherals. • DMA operations can optionally be triggered by on- or off-chip events. • Priority is user selectable for each channel. • Continuous priority arbitration. • Address cache. • Efficient use of data bus. • Supports single transfers up to 1,024 words. • Address increment options allow packing and/or unpacking data. 10.19.2 DMIC subsystem 10.19.2.1 Features • Pulse-Density Modulation (PDM) data input for left and/or right channels on 1 or 2 buses. • Flexible decimation. • 16 entry FIFO for each channel. • DC blocking or unaltered DC bias can be selected. |
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